b22562b765cf1259a81da77316772302caee9975.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company:			Han's laser 
-- Engineer:  		Zhouj110624
-- Create Date:    	09:57:48 10/08/2012 
-- Design Name:		decod_state 
-- Module Name:    	decod_state - Behavioral 
-- Project Name: 	coding_crc
-- Target Devices: 	XC2C128-6VQ100
-- 功能说明：此状态机模块包含三个状态，即初始状态idle、编码状态cod、erro
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity decod_state is
	 Port ( CLK 								: in  STD_LOGIC;
			  RST									: in	std_logic;
			  DECODE_ERROR						: in	STD_LOGIC;
			  MANCHESTER						: in 	STD_LOGIC;	--输入含同步头的曼切斯特码
			  DETECTION							: out std_logic;
			  MANCHESTER_WITHOUT_HEADER	: out STD_LOGIC;	--去除同步头后的曼切斯特码
			  DECODE_EN		 					: out STD_LOGIC	--编码使能输出
			 );
end decod_state;

architecture Behavioral of decod_state is

	signal now_state,next_state : std_logic_vector(2 downto 0) := "001";
	constant idle	:	std_logic_vector(2 downto 0) := "001";
	constant decod	:	std_logic_vector(2 downto 0) := "010";
	constant error	:	std_logic_vector(2 downto 0) := "100";
	signal head_count_flag		:	std_logic := '0';--计数反馈信号
	signal decode_end				:	std_logic := '0';
	signal decode_cnt_en			:	std_logic := '0';
	signal manchester_reg		:	std_logic := '0';
--	signal port_mistake			:	std_logic := '0';
--	signal CLK_div					:	std_logic := '0';
	signal head_cnt				:	std_logic_vector( 4 downto 0 ) := (others => '0');--时钟计数，用于去除同步头
	signal decode_cnt				:	std_logic_vector( 7 downto 0 ) := (others => '0');--时钟计数，对曼切斯特码总长计数
--	signal detcetion_cnt			:	std_logic_vector( 7 downto 0 ) := (others => '0');--时钟计数，用于检测接口
--	signal CLK_div_cnt			:	std_logic_vector(3 downto 0) := (others => '0');

begin
				
	Pr_D	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			manchester_reg <= MANCHESTER;
		end if;
	end process;
----------------------------------------------------------------------------------
--时钟计数进程,Pr_count：去除同步头前的曼切斯特码高电平使能；
----------------------------------------------------------------------------------	
	Pr_start	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			if RST = '1' then
				head_count_flag <= '0';
				head_cnt <= (others => '0');
			else
				if  manchester_reg = '1' then
					head_cnt <= head_cnt + 1;
					--对曼切斯特码同步头的计数，达到"11110"，说明这个为同步头，并输出反馈信号,30
					if head_cnt = "11110" then
						head_count_flag <= '1';
					else
						head_count_flag <= '0';
					end if;
				else
					head_count_flag <= '0';
					head_cnt <= (others => '0');
				end if;
			end if;
		end if;
	end process;

	Pr_end	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			if RST = '1' then
				decode_cnt <= (others => '0');
				decode_end <= '0';
			else
				if decode_cnt_en	= '0' then
					decode_cnt <= (others => '0');
					decode_end <= '0';
				else
					--通过计数来确定解码完成，要根据串行码的位数计算
					--每个编码时间t=80ns乘以位数w=28，等于2240ns及约为224个10ns的时钟周期，此处取222
					if decode_cnt <= "11100110" then 
						decode_cnt <= decode_cnt + 1;
						decode_end <= '0';
					else
						decode_cnt <= (others => '0');
						decode_end <= '1';
					end if;
				end if;
			end if;
		end if;
	end process;
					
	Pr_reg	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			now_state <= next_state;
		end if;
	end process;
				
	Pr_com	:	
	process(RST,now_state,head_count_flag,decode_end,DECODE_ERROR)
	begin
		if RST = '1' then
			next_state <= idle;
		else
		case now_state is
			--初始状态，空闲状态， 
			when idle	=>
				--检测到同步头时，进入decoding状态
				if DECODE_ERROR = '1' then
					next_state <= error;
				elsif head_count_flag = '1' then	
					next_state <= decod;
				else
					next_state <= idle;
				end if;
			--解码状态
			when decod	=>
				if DECODE_ERROR = '1' then
					next_state <= error;
				elsif decode_end = '1' then
					next_state <= idle;
				else
					next_state <= decod;
				end if;
			when error	=>
				if head_count_flag = '1' then	
					next_state <= decod;
				else
					next_state <= error;
				end if;
			when others	=> next_state <= idle;
		end case;
		end if;
	end process;
	
	DECODE_EN <= decode_cnt_en;
	Pr_out	:	
	process(CLK)	
	begin
		if rising_edge(CLK) then
			case now_state is
				when	idle	=>
					decode_cnt_en <= '0';
					MANCHESTER_WITHOUT_HEADER <= '0';
					DETECTION <= '0';
				when	decod 	=>
					DETECTION <= '0';
					decode_cnt_en <= '1';
					MANCHESTER_WITHOUT_HEADER <= MANCHESTER;
				when 	error	=>
					decode_cnt_en <= '0';
					MANCHESTER_WITHOUT_HEADER <= '0'; 
					DETECTION <= '1';
				when	others => 
					decode_cnt_en <= '0';
					MANCHESTER_WITHOUT_HEADER <= '0';
					DETECTION <= '0';
			end case;
		end if;
	end process;
				
end Behavioral;