4525d7ac1f1d865b06d08e8fcc12726c37830dbf.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

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-- Company: 
-- Engineer:
--
-- Create Date:   15:40:51 01/28/2013
-- Design Name:   
-- Module Name:   D:/FpgaProgram/G510-106T/G510_106T_add_1_25_pm/tb_pwm_12.vhd
-- Project Name:  G510_106T_1_1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: pwm_12
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_pwm_12 IS
END tb_pwm_12;
 
ARCHITECTURE behavior OF tb_pwm_12 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT pwm_12
    PORT(
         Clk : IN  std_logic;
         Pid_duty_fre : IN  std_logic_vector(31 downto 0);
         Pia_chan : IN  std_logic_vector(10 downto 0);
			Clk_out		:	out	std_logic;
			data_d			:	out	std_logic_vector(13 downto 0);
			data_f			:	out	std_logic_vector(15 downto 0);
         Poc_dir_p : OUT  std_logic_vector(11 downto 0);
         Poc_dir_n : OUT  std_logic_vector(11 downto 0);
         Poc_pwm : OUT  std_logic_vector(11 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';
   signal Pid_duty_fre : std_logic_vector(31 downto 0) := (others => '0');
   signal Pia_chan : std_logic_vector(10 downto 0) := (others => '0');

 	--Outputs
   signal Poc_dir_p : std_logic_vector(11 downto 0);
   signal Poc_dir_n : std_logic_vector(11 downto 0);
   signal Poc_pwm : std_logic_vector(11 downto 0);
	signal Clk_out		:		std_logic;
	signal data_d			:		std_logic_vector(13 downto 0);
	signal data_f			:		std_logic_vector(15 downto 0);
   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: pwm_12 PORT MAP (
          Clk => Clk, 
			 Clk_out => Clk_out,
			 data_d => data_d,
			 data_f => data_f,
          Pid_duty_fre => Pid_duty_fre,
          Pia_chan => Pia_chan,
          Poc_dir_p => Poc_dir_p,
          Poc_dir_n => Poc_dir_n,
          Poc_pwm => Poc_pwm
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for Clk_period*10;
		Pid_duty_fre <= x"07d303e8";
		Pia_chan <= "10000100000";
      -- insert stimulus here 

      wait; 
   end process;

END;