📄 a13148ee34f801eb47bdf86d7e9d37269d31cdea.svn-base
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------------------------------------------------------------------------------------ Company: hanslase PEM-- Engineer: tanzewei-- -- Create Date: 10:00:48 04/07/2011 -- Design Name: -- Module Name: quad_encoder - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity quad_encoder is
Port (
CLK : in std_logic;
RST : in std_logic;
CLEAR_CNT : in std_logic;
CODER_QEA : in std_logic;
CODER_QEB : in std_logic;
-- data_z : in std_logic;
-- Poc_pulse : out std_logic;
-- Poc_dir : out std_logic;
CODER_CNT_OUT : out std_logic_vector (31 downto 0)
);
end quad_encoder;
architecture behav of quad_encoder is
signal CODER_QEA_delay : std_logic_vector(1 downto 0);
signal CODER_QEB_delay : std_logic_vector(1 downto 0);
--signal data_z_delay : std_logic_vector(1 downto 0);
signal CODER_QEA_af : std_logic_vector(1 downto 0); -- af means after filter
signal CODER_QEB_af : std_logic_vector(1 downto 0); -- af means after filter
--signal data_z_af : std_logic_vector(1 downto 0); -- af means after filter
--- logic filter comonent and related signals declaration following here
--constant logic_filter_th_hi : std_logic_vector(3 downto 0) := "1000";
constant logic_filter_th_hi : std_logic_vector(1 downto 0) := "10";
component log_filter is
generic(
TH_WIDTH : integer := 6
);
port(
CLK : in std_logic;
RST : in std_logic;
data_in : in std_logic;
th_hi : in std_logic_vector(TH_WIDTH-1 downto 0);
data_out: out std_logic
);
end component;
--- decoding related signals following here
signal cnt_en : std_logic; --- cnt_en means count enable
signal cnt_dir : std_logic; ---
--signal cnt_dir_reg : std_logic;
signal CLEAR_CNT_d0 : std_logic;
signal CLEAR_CNT_pulse : std_logic;
signal CODER_CNT_OUT_reg : std_logic_vector(31 downto 0);
begin
-- Poc_pulse <= cnt_en;
-- Poc_dir <= cnt_dir_reg ;
--- synchronization process following here
process(CLK)
begin
if(CLK' event and CLK = '1')then
if(RST = '1')then
CODER_QEA_delay <= CODER_QEA&CODER_QEA;
else
CODER_QEA_delay <= CODER_QEA_delay(0)&CODER_QEA;
end if;
end if;
end process;
--- synchroning data b
process(CLK)
begin
if(CLK' event and CLK = '1')then
if(RST = '1')then
CODER_QEB_delay <= CODER_QEB&CODER_QEB;
else
CODER_QEB_delay <= CODER_QEB_delay(0)&CODER_QEB;
end if;
end if;
end process;
--- synchroning data z
-- process(CLK)
-- begin
-- if(CLK' event and CLK = '1')then
-- if(RST = '1')then
-- data_z_delay <= data_z&data_z;
-- else
-- data_z_delay <= data_z_delay(0)&data_z;
-- end if;
-- end if;
-- end process;
----filter signal a b z for stablization
log_filter_insta : log_filter
generic map(
TH_WIDTH => 2 --- 25MHz/10, pulse width less than 10*40ns will be discarded
)
port map(
CLK => CLK,
RST => RST,
data_in => CODER_QEA_delay(1),
th_hi => logic_filter_th_hi,
data_out=> CODER_QEA_af(0)
);
log_filter_instb : log_filter
generic map(
TH_WIDTH => 2 --- 25MHz/10, pulse width less than 10*40ns will be discarded
)
port map(
CLK => CLK,
RST => RST,
data_in => CODER_QEB_delay(1),
th_hi => logic_filter_th_hi,
data_out=> CODER_QEB_af(0)
);
--log_filter_instz : log_filter
-- generic map(
-- TH_WIDTH => 2 --- 25MHz/10, pulse width less than 10*40ns will be discarded
-- )
-- port map(
-- CLK => CLK,
-- RST => RST,
-- data_in => data_z_delay(1),
-- th_hi => logic_filter_th_hi,
-- data_out=> data_z_af(0)
-- );
-- CODER_QEA_af(0) <= CODER_QEA_delay(1);
-- CODER_QEB_af(0) <= CODER_QEB_delay(1);
-- data_z_af(0) <= data_z_delay(1);
--- delayed abz after logic filter-
-- process a
process(CLK)
begin
if(CLK' event and CLK = '1')then
if(RST = '1')then
CODER_QEA_af(1) <= CODER_QEA;
else
CODER_QEA_af(1) <= CODER_QEA_af(0);
end if;
end if;
end process;
---process b
process(CLK)
begin
if(CLK' event and CLK = '1')then
if(RST = '1')then
CODER_QEB_af(1) <= CODER_QEB;
else
CODER_QEB_af(1) <= CODER_QEB_af(0);
end if;
end if;
end process;
---process c
-- process(CLK)
-- begin
-- if(CLK' event and CLK = '1')then
-- if(RST = '1')then
-- data_z_af(1) <= data_z;
-- else
-- data_z_af(1) <= data_z_af(0);
-- end if;
-- end if;
-- end process;
--- main process for decoding following here
cnt_en <= ((CODER_QEA_af(0) xor CODER_QEA_af(1))and(CODER_QEB_af(0) xnor CODER_QEB_af(1))) or ((CODER_QEA_af(0) xnor CODER_QEA_af(1))and(CODER_QEB_af(0) xor CODER_QEB_af(1)));
cnt_dir <= (CODER_QEA_af(1) and CODER_QEA_af(0) and (not CODER_QEB_af(1)) and CODER_QEB_af(0)) or (CODER_QEA_af(1) and (not CODER_QEA_af(0)) and CODER_QEB_af(1) and CODER_QEB_af(0)) or ((not CODER_QEA_af(1)) and (not CODER_QEA_af(0)) and CODER_QEB_af(1) and (not CODER_QEB_af(0))) or ((not CODER_QEA_af(1)) and CODER_QEA_af(0) and (not CODER_QEB_af(1)) and (not CODER_QEB_af(0)));
---- a(1)-a(0)-b(1)-b(0) --- 1101 or 1011 or 0010 or 0100
---
-- process(CLK)
-- begin
-- if(CLK' event and CLK = '1')then
-- if(RST = '1')then
-- cnt_dir_reg <= '0';
-- else
-- if(cnt_en = '1')then
-- cnt_dir_reg <= cnt_dir;
-- else
-- cnt_dir_reg <= cnt_dir_reg;
-- end if;
-- end if;
-- end if;
-- end process;
--- count register clear pulse generation process;
process(CLK)
begin
if(CLK' event and CLK = '1')then
CLEAR_CNT_d0 <= CLEAR_CNT;
end if;
end process;
CLEAR_CNT_pulse <= (not CLEAR_CNT_d0) and CLEAR_CNT ;
--- count process;
process(CLK)
begin
if(CLK' event and CLK = '1')then
if(RST = '1')then
CODER_CNT_OUT_reg <= (others => '0');
else
-- if(CLEAR_CNT_pulse = '1' or data_z_af(1) = '1')then
if(CLEAR_CNT_pulse = '1')then
CODER_CNT_OUT_reg <= (others => '0');
else
case cnt_en is
when '1' =>
case cnt_dir is
when '1' => CODER_CNT_OUT_reg <= CODER_CNT_OUT_reg + 1;
when '0' => CODER_CNT_OUT_reg <= CODER_CNT_OUT_reg - 1;
when others => CODER_CNT_OUT_reg <= CODER_CNT_OUT_reg;
end case;
when others => CODER_CNT_OUT_reg <= CODER_CNT_OUT_reg;
end case;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(CLK' event and CLK = '1')then
CODER_CNT_OUT <= CODER_CNT_OUT_reg;
end if;
end process;
-- CODER_CNT_OUT <= CODER_CNT_OUT_reg;
end behav;
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