a1503dfd652324b8541ced548e0e7e705a099dae.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
sram YourInstanceName (
	.clka(clka),
	.ena(ena),
	.wea(wea), // Bus [0 : 0] 
	.addra(addra), // Bus [10 : 0] 
	.dina(dina), // Bus [31 : 0] 
	.clkb(clkb),
	.enb(enb),
	.addrb(addrb), // Bus [11 : 0] 
	.doutb(doutb)); // Bus [15 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file sram.v when simulating
// the core, sram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".