transfer.vhd

来自「EDA实验--UART串口实验：UART 主要有由数据总线接口、控制逻辑、波特率」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;

entity transfer is
    port(clk,reset,start : in std_logic;
         txd,txddone     : out std_logic);
end transfer;

architecture behave of transfer is
component baud
    port(clk,resetb : in std_logic;
         bclk       : out std_logic);
end component;
component txmit
    port(bclkt,resett,xmit_cmd_p : in std_logic;
         txd,txd_done            : out std_logic);
end component;
signal bclk:std_logic;
begin
  U1:baud  port map ( clk , reset , bclk );
  U2:txmit port map ( bclk, reset , start , txd, txddone );
end behave;