decoder_3_8.v

用VERILOG语言实现了常用3-8译码器.

module  Decoder_3_8(G1,G2A,G2B,C,B,A,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0);
input   G1,G2A,G2B;
input   C,B,A;
output  Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0;

reg  Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0;

always  @(G1 or G2A or G2B or C or B or A)
begin
  if((G1 == 1'b0) || (G2A == 1'b1) || (G2B == 1'b1))
    {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11111111;
  else if ((G1 == 1'b1) && (G2A == 1'b0) && (G2B == 1'b0))
    begin
      case({C,B,A})
        3'b000  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11111110;
        3'b001  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11111101;
        3'b010  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11111011;
        3'b011  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11110111;
        3'b100  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11101111;
        3'b101  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11011111;
        3'b110  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b10111111;
        3'b111  :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b01111111;
        default :  {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11111111;
      endcase
    end
  else
    {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} <= 8'b11111111;
end

endmodule