decoder_3_8.map.summary

用VERILOG语言实现了常用3-8译码器.

Flow Status : Successful - Tue Aug 08 10:06:17 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Decoder_3_8
Top-level Entity Name : Decoder_3_8
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 8
Total pins : 14