compare_8_bits.hier_info

用VERILOG语言实现了8BIT编码器.

|Compare_8_bits
A[0] => always0~0.IN0
A[0] => LessThan~0.IN8
A[0] => LessThan~1.IN8
A[1] => always0~1.IN0
A[1] => LessThan~0.IN7
A[1] => LessThan~1.IN7
A[2] => always0~2.IN0
A[2] => LessThan~0.IN6
A[2] => LessThan~1.IN6
A[3] => always0~3.IN0
A[3] => LessThan~0.IN5
A[3] => LessThan~1.IN5
A[4] => always0~4.IN0
A[4] => LessThan~0.IN4
A[4] => LessThan~1.IN4
A[5] => always0~5.IN0
A[5] => LessThan~0.IN3
A[5] => LessThan~1.IN3
A[6] => always0~6.IN0
A[6] => LessThan~0.IN2
A[6] => LessThan~1.IN2
A[7] => always0~7.IN0
A[7] => LessThan~0.IN1
A[7] => LessThan~1.IN1
B[0] => always0~0.IN1
B[0] => LessThan~0.IN16
B[0] => LessThan~1.IN16
B[1] => always0~1.IN1
B[1] => LessThan~0.IN15
B[1] => LessThan~1.IN15
B[2] => always0~2.IN1
B[2] => LessThan~0.IN14
B[2] => LessThan~1.IN14
B[3] => always0~3.IN1
B[3] => LessThan~0.IN13
B[3] => LessThan~1.IN13
B[4] => always0~4.IN1
B[4] => LessThan~0.IN12
B[4] => LessThan~1.IN12
B[5] => always0~5.IN1
B[5] => LessThan~0.IN11
B[5] => LessThan~1.IN11
B[6] => always0~6.IN1
B[6] => LessThan~0.IN10
B[6] => LessThan~1.IN10
B[7] => always0~7.IN1
B[7] => LessThan~0.IN9
B[7] => LessThan~1.IN9
EQ <= EQ~0.DB_MAX_OUTPUT_PORT_TYPE
GT <= GT~0.DB_MAX_OUTPUT_PORT_TYPE
LT <= LT~1.DB_MAX_OUTPUT_PORT_TYPE