compare_8_bits.v

用VERILOG语言实现了8BIT编码器.

module  Compare_8_bits(A,B,EQ,GT,LT);
input   [7:0] A,B;
output  EQ,GT,LT;

reg  EQ,GT,LT;

always  @(A or B)

begin
  if(A == B)
    {EQ,GT,LT}  <=  3'b100;
  else if(A > B)
    {EQ,GT,LT}  <=  3'b010;
  else if(A < B)
    {EQ,GT,LT}  <=  3'b001;
  else
    {EQ,GT,LT}  <=  3'b000;
end

endmodule