compare_8_bits.map.summary

来自「用VERILOG语言实现了8BIT编码器.」· SUMMARY 代码 · 共 9 行

Flow Status : Successful - Tue Aug 08 13:27:27 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Compare_8_bits
Top-level Entity Name : Compare_8_bits
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 19
Total pins : 19