compare_8_bits.fit.summary

用VERILOG语言实现了8BIT编码器.

Flow Status : Successful - Tue Aug 08 13:27:30 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Compare_8_bits
Top-level Entity Name : Compare_8_bits
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 19 / 32 ( 59 % )
Total pins : 23 / 36 ( 63 % )
Device : EPM7032SLC44-5
Timing Models : Final