fsk.tan.qmsg

用vhdl写的fpga移频键控程序

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "PL_FSK2:inst12\|q\[0\] PL_FSK2:inst12\|cnt\[0\] clk 465 ps " "Info: Found hold time violation between source  pin or register \"PL_FSK2:inst12\|q\[0\]\" and destination pin or register \"PL_FSK2:inst12\|cnt\[0\]\" for clock \"clk\" (Hold time is 465 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.590 ns + Largest " "Info: + Largest clock skew is 2.590 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.920 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.970 ns) 2.634 ns PL_FSK2:inst12\|regs 2 REG LCFF_X1_Y6_N17 1 " "Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N17; Fanout = 1; REG Node = 'PL_FSK2:inst12\|regs'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { clk PL_FSK2:inst12|regs } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.808 ns) + CELL(0.000 ns) 3.442 ns PL_FSK2:inst12\|regs~clkctrl 3 COMB CLKCTRL_G1 3 " "Info: 3: + IC(0.808 ns) + CELL(0.000 ns) = 3.442 ns; Loc. = CLKCTRL_G1; Fanout = 3; COMB Node = 'PL_FSK2:inst12\|regs~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.808 ns" { PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.666 ns) 4.920 ns PL_FSK2:inst12\|cnt\[0\] 4 REG LCFF_X1_Y6_N19 3 " "Info: 4: + IC(0.812 ns) + CELL(0.666 ns) = 4.920 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 3; REG Node = 'PL_FSK2:inst12\|cnt\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.478 ns" { PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[0] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 56.42 % ) " "Info: Total cell delay = 2.776 ns ( 56.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.144 ns ( 43.58 % ) " "Info: Total interconnect delay = 2.144 ns ( 43.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { clk PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.920 ns" { clk {} clk~combout {} PL_FSK2:inst12|regs {} PL_FSK2:inst12|regs~clkctrl {} PL_FSK2:inst12|cnt[0] {} } { 0.000ns 0.000ns 0.524ns 0.808ns 0.812ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.330 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.666 ns) 2.330 ns PL_FSK2:inst12\|q\[0\] 2 REG LCFF_X1_Y6_N25 6 " "Info: 2: + IC(0.524 ns) + CELL(0.666 ns) = 2.330 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 6; REG Node = 'PL_FSK2:inst12\|q\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.190 ns" { clk PL_FSK2:inst12|q[0] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 77.51 % ) " "Info: Total cell delay = 1.806 ns ( 77.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.524 ns ( 22.49 % ) " "Info: Total interconnect delay = 0.524 ns ( 22.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.330 ns" { clk PL_FSK2:inst12|q[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.330 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[0] {} } { 0.000ns 0.000ns 0.524ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { clk PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.920 ns" { clk {} clk~combout {} PL_FSK2:inst12|regs {} PL_FSK2:inst12|regs~clkctrl {} PL_FSK2:inst12|cnt[0] {} } { 0.000ns 0.000ns 0.524ns 0.808ns 0.812ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.330 ns" { clk PL_FSK2:inst12|q[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.330 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[0] {} } { 0.000ns 0.000ns 0.524ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.127 ns - Shortest register register " "Info: - Shortest register to register delay is 2.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PL_FSK2:inst12\|q\[0\] 1 REG LCFF_X1_Y6_N25 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 6; REG Node = 'PL_FSK2:inst12\|q\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PL_FSK2:inst12|q[0] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.202 ns) 0.947 ns PL_FSK2:inst12\|Equal1~17 2 COMB LCCOMB_X1_Y6_N20 4 " "Info: 2: + IC(0.745 ns) + CELL(0.202 ns) = 0.947 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 4; COMB Node = 'PL_FSK2:inst12\|Equal1~17'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.947 ns" { PL_FSK2:inst12|q[0] PL_FSK2:inst12|Equal1~17 } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.421 ns) + CELL(0.651 ns) 2.019 ns PL_FSK2:inst12\|cnt\[0\]~152 3 COMB LCCOMB_X1_Y6_N18 1 " "Info: 3: + IC(0.421 ns) + CELL(0.651 ns) = 2.019 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 1; COMB Node = 'PL_FSK2:inst12\|cnt\[0\]~152'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.072 ns" { PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|cnt[0]~152 } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.127 ns PL_FSK2:inst12\|cnt\[0\] 4 REG LCFF_X1_Y6_N19 3 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.127 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 3; REG Node = 'PL_FSK2:inst12\|cnt\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { PL_FSK2:inst12|cnt[0]~152 PL_FSK2:inst12|cnt[0] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.961 ns ( 45.18 % ) " "Info: Total cell delay = 0.961 ns ( 45.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.166 ns ( 54.82 % ) " "Info: Total interconnect delay = 1.166 ns ( 54.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.127 ns" { PL_FSK2:inst12|q[0] PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|cnt[0]~152 PL_FSK2:inst12|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.127 ns" { PL_FSK2:inst12|q[0] {} PL_FSK2:inst12|Equal1~17 {} PL_FSK2:inst12|cnt[0]~152 {} PL_FSK2:inst12|cnt[0] {} } { 0.000ns 0.745ns 0.421ns 0.000ns } { 0.000ns 0.202ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { clk PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.920 ns" { clk {} clk~combout {} PL_FSK2:inst12|regs {} PL_FSK2:inst12|regs~clkctrl {} PL_FSK2:inst12|cnt[0] {} } { 0.000ns 0.000ns 0.524ns 0.808ns 0.812ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.330 ns" { clk PL_FSK2:inst12|q[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.330 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[0] {} } { 0.000ns 0.000ns 0.524ns } { 0.000ns 1.140ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.127 ns" { PL_FSK2:inst12|q[0] PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|cnt[0]~152 PL_FSK2:inst12|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.127 ns" { PL_FSK2:inst12|q[0] {} PL_FSK2:inst12|Equal1~17 {} PL_FSK2:inst12|cnt[0]~152 {} PL_FSK2:inst12|cnt[0] {} } { 0.000ns 0.745ns 0.421ns 0.000ns } { 0.000ns 0.202ns 0.651ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "PL_FSK:inst\|f1 start1 clk 5.884 ns register " "Info: tsu for register \"PL_FSK:inst\|f1\" (data pin = \"start1\", clock pin = \"clk\") is 5.884 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.684 ns + Longest pin register " "Info: + Longest pin to register delay is 8.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns start1 1 PIN PIN_173 7 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_173; Fanout = 7; PIN Node = 'start1'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start1 } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 144 -48 120 160 "start1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.865 ns) + CELL(0.855 ns) 8.684 ns PL_FSK:inst\|f1 2 REG LCFF_X2_Y6_N13 1 " "Info: 2: + IC(6.865 ns) + CELL(0.855 ns) = 8.684 ns; Loc. = LCFF_X2_Y6_N13; Fanout = 1; REG Node = 'PL_FSK:inst\|f1'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.720 ns" { start1 PL_FSK:inst|f1 } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.819 ns ( 20.95 % ) " "Info: Total cell delay = 1.819 ns ( 20.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.865 ns ( 79.05 % ) " "Info: Total interconnect delay = 6.865 ns ( 79.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.684 ns" { start1 PL_FSK:inst|f1 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.684 ns" { start1 {} start1~combout {} PL_FSK:inst|f1 {} } { 0.000ns 0.000ns 6.865ns } { 0.000ns 0.964ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.760 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.666 ns) 2.760 ns PL_FSK:inst\|f1 3 REG LCFF_X2_Y6_N13 1 " "Info: 3: + IC(0.811 ns) + CELL(0.666 ns) = 2.760 ns; Loc. = LCFF_X2_Y6_N13; Fanout = 1; REG Node = 'PL_FSK:inst\|f1'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { clk~clkctrl PL_FSK:inst|f1 } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.43 % ) " "Info: Total cell delay = 1.806 ns ( 65.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.954 ns ( 34.57 % ) " "Info: Total interconnect delay = 0.954 ns ( 34.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl PL_FSK:inst|f1 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} PL_FSK:inst|f1 {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.684 ns" { start1 PL_FSK:inst|f1 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.684 ns" { start1 {} start1~combout {} PL_FSK:inst|f1 {} } { 0.000ns 0.000ns 6.865ns } { 0.000ns 0.964ns 0.855ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl PL_FSK:inst|f1 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} PL_FSK:inst|f1 {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk demodul_signal PL_FSK2:inst12\|B_S 8.961 ns register " "Info: tco from clock \"clk\" to destination pin \"demodul_signal\" through register \"PL_FSK2:inst12\|B_S\" is 8.961 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.813 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.813 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.970 ns) 2.634 ns PL_FSK2:inst12\|q\[1\] 2 REG LCFF_X1_Y6_N13 5 " "Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N13; Fanout = 5; REG Node = 'PL_FSK2:inst12\|q\[1\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { clk PL_FSK2:inst12|q[1] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.490 ns) + CELL(0.651 ns) 3.775 ns PL_FSK2:inst12\|Equal1~17 3 COMB LCCOMB_X1_Y6_N20 4 " "Info: 3: + IC(0.490 ns) + CELL(0.651 ns) = 3.775 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 4; COMB Node = 'PL_FSK2:inst12\|Equal1~17'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { PL_FSK2:inst12|q[1] PL_FSK2:inst12|Equal1~17 } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.615 ns) 4.813 ns PL_FSK2:inst12\|B_S 4 REG LCCOMB_X1_Y6_N22 1 " "Info: 4: + IC(0.423 ns) + CELL(0.615 ns) = 4.813 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12\|B_S'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.038 ns" { PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|B_S } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.376 ns ( 70.14 % ) " "Info: Total cell delay = 3.376 ns ( 70.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.437 ns ( 29.86 % ) " "Info: Total interconnect delay = 1.437 ns ( 29.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.813 ns" { clk PL_FSK2:inst12|q[1] PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|B_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.813 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[1] {} PL_FSK2:inst12|Equal1~17 {} PL_FSK2:inst12|B_S {} } { 0.000ns 0.000ns 0.524ns 0.490ns 0.423ns } { 0.000ns 1.140ns 0.970ns 0.651ns 0.615ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.148 ns + Longest register pin " "Info: + Longest register to pin delay is 4.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PL_FSK2:inst12\|B_S 1 REG LCCOMB_X1_Y6_N22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12\|B_S'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PL_FSK2:inst12|B_S } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.052 ns) + CELL(3.096 ns) 4.148 ns demodul_signal 2 PIN PIN_33 0 " "Info: 2: + IC(1.052 ns) + CELL(3.096 ns) = 4.148 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'demodul_signal'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.148 ns" { PL_FSK2:inst12|B_S demodul_signal } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 96 504 680 112 "demodul_signal" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 74.64 % ) " "Info: Total cell delay = 3.096 ns ( 74.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.052 ns ( 25.36 % ) " "Info: Total interconnect delay = 1.052 ns ( 25.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.148 ns" { PL_FSK2:inst12|B_S demodul_signal } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.148 ns" { PL_FSK2:inst12|B_S {} demodul_signal {} } { 0.000ns 1.052ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.813 ns" { clk PL_FSK2:inst12|q[1] PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|B_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.813 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[1] {} PL_FSK2:inst12|Equal1~17 {} PL_FSK2:inst12|B_S {} } { 0.000ns 0.000ns 0.524ns 0.490ns 0.423ns } { 0.000ns 1.140ns 0.970ns 0.651ns 0.615ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.148 ns" { PL_FSK2:inst12|B_S demodul_signal } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.148 ns" { PL_FSK2:inst12|B_S {} demodul_signal {} } { 0.000ns 1.052ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "PL_FSK:inst\|M_S modul_signal clk -4.552 ns register " "Info: th for register \"PL_FSK:inst\|M_S\" (data pin = \"modul_signal\", clock pin = \"clk\") is -4.552 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.760 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.666 ns) 2.760 ns PL_FSK:inst\|M_S 3 REG LCFF_X2_Y6_N31 1 " "Info: 3: + IC(0.811 ns) + CELL(0.666 ns) = 2.760 ns; Loc. = LCFF_X2_Y6_N31; Fanout = 1; REG Node = 'PL_FSK:inst\|M_S'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { clk~clkctrl PL_FSK:inst|M_S } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.43 % ) " "Info: Total cell delay = 1.806 ns ( 65.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.954 ns ( 34.57 % ) " "Info: Total interconnect delay = 0.954 ns ( 34.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl PL_FSK:inst|M_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} PL_FSK:inst|M_S {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.618 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 0.975 ns modul_signal 1 PIN PIN_10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.975 ns) = 0.975 ns; Loc. = PIN_10; Fanout = 1; PIN Node = 'modul_signal'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { modul_signal } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 160 -48 120 176 "modul_signal" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.329 ns) + CELL(0.206 ns) 7.510 ns PL_FSK:inst\|M_S~10 2 COMB LCCOMB_X2_Y6_N30 1 " "Info: 2: + IC(6.329 ns) + CELL(0.206 ns) = 7.510 ns; Loc. = LCCOMB_X2_Y6_N30; Fanout = 1; COMB Node = 'PL_FSK:inst\|M_S~10'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.535 ns" { modul_signal PL_FSK:inst|M_S~10 } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.618 ns PL_FSK:inst\|M_S 3 REG LCFF_X2_Y6_N31 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.618 ns; Loc. = LCFF_X2_Y6_N31; Fanout = 1; REG Node = 'PL_FSK:inst\|M_S'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { PL_FSK:inst|M_S~10 PL_FSK:inst|M_S } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.289 ns ( 16.92 % ) " "Info: Total cell delay = 1.289 ns ( 16.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.329 ns ( 83.08 % ) " "Info: Total interconnect delay = 6.329 ns ( 83.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.618 ns" { modul_signal PL_FSK:inst|M_S~10 PL_FSK:inst|M_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.618 ns" { modul_signal {} modul_signal~combout {} PL_FSK:inst|M_S~10 {} PL_FSK:inst|M_S {} } { 0.000ns 0.000ns 6.329ns 0.000ns } { 0.000ns 0.975ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl PL_FSK:inst|M_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} PL_FSK:inst|M_S {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.618 ns" { modul_signal PL_FSK:inst|M_S~10 PL_FSK:inst|M_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.618 ns" { modul_signal {} modul_signal~combout {} PL_FSK:inst|M_S~10 {} PL_FSK:inst|M_S {} } { 0.000ns 0.000ns 6.329ns 0.000ns } { 0.000ns 0.975ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}