fsk.tan.qmsg

用vhdl写的fpga移频键控程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst12\|q\[1\] " "Info: Detected ripple clock \"PL_FSK2:inst12\|q\[1\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst12\|q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst12\|q\[0\] " "Info: Detected ripple clock \"PL_FSK2:inst12\|q\[0\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst12\|q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst12\|q\[2\] " "Info: Detected ripple clock \"PL_FSK2:inst12\|q\[2\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst12\|q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst12\|q\[3\] " "Info: Detected ripple clock \"PL_FSK2:inst12\|q\[3\]\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst12\|q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "PL_FSK2:inst12\|Equal1~17 " "Info: Detected gated clock \"PL_FSK2:inst12\|Equal1~17\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 37 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst12\|Equal1~17" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "PL_FSK2:inst12\|regs " "Info: Detected ripple clock \"PL_FSK2:inst12\|regs\" as buffer" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 17 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "PL_FSK2:inst12\|regs" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register PL_FSK2:inst12\|cnt\[2\] register PL_FSK2:inst12\|B_S 174.4 MHz 5.734 ns Internal " "Info: Clock \"clk\" has Internal fmax of 174.4 MHz between source register \"PL_FSK2:inst12\|cnt\[2\]\" and destination register \"PL_FSK2:inst12\|B_S\" (period= 5.734 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.649 ns + Longest register register " "Info: + Longest register to register delay is 0.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PL_FSK2:inst12\|cnt\[2\] 1 REG LCFF_X1_Y6_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N3; Fanout = 2; REG Node = 'PL_FSK2:inst12\|cnt\[2\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PL_FSK2:inst12|cnt[2] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.206 ns) 0.649 ns PL_FSK2:inst12\|B_S 2 REG LCCOMB_X1_Y6_N22 1 " "Info: 2: + IC(0.443 ns) + CELL(0.206 ns) = 0.649 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12\|B_S'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.649 ns" { PL_FSK2:inst12|cnt[2] PL_FSK2:inst12|B_S } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.206 ns ( 31.74 % ) " "Info: Total cell delay = 0.206 ns ( 31.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.443 ns ( 68.26 % ) " "Info: Total interconnect delay = 0.443 ns ( 68.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.649 ns" { PL_FSK2:inst12|cnt[2] PL_FSK2:inst12|B_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "0.649 ns" { PL_FSK2:inst12|cnt[2] {} PL_FSK2:inst12|B_S {} } { 0.000ns 0.443ns } { 0.000ns 0.206ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.301 ns - Smallest " "Info: - Smallest clock skew is -0.301 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.619 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.970 ns) 2.634 ns PL_FSK2:inst12\|q\[0\] 2 REG LCFF_X1_Y6_N25 6 " "Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 6; REG Node = 'PL_FSK2:inst12\|q\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { clk PL_FSK2:inst12|q[0] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.202 ns) 3.581 ns PL_FSK2:inst12\|Equal1~17 3 COMB LCCOMB_X1_Y6_N20 4 " "Info: 3: + IC(0.745 ns) + CELL(0.202 ns) = 3.581 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 4; COMB Node = 'PL_FSK2:inst12\|Equal1~17'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.947 ns" { PL_FSK2:inst12|q[0] PL_FSK2:inst12|Equal1~17 } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.615 ns) 4.619 ns PL_FSK2:inst12\|B_S 4 REG LCCOMB_X1_Y6_N22 1 " "Info: 4: + IC(0.423 ns) + CELL(0.615 ns) = 4.619 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12\|B_S'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.038 ns" { PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|B_S } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.927 ns ( 63.37 % ) " "Info: Total cell delay = 2.927 ns ( 63.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.692 ns ( 36.63 % ) " "Info: Total interconnect delay = 1.692 ns ( 36.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.619 ns" { clk PL_FSK2:inst12|q[0] PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|B_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.619 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[0] {} PL_FSK2:inst12|Equal1~17 {} PL_FSK2:inst12|B_S {} } { 0.000ns 0.000ns 0.524ns 0.745ns 0.423ns } { 0.000ns 1.140ns 0.970ns 0.202ns 0.615ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.920 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 4.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.970 ns) 2.634 ns PL_FSK2:inst12\|regs 2 REG LCFF_X1_Y6_N17 1 " "Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N17; Fanout = 1; REG Node = 'PL_FSK2:inst12\|regs'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { clk PL_FSK2:inst12|regs } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.808 ns) + CELL(0.000 ns) 3.442 ns PL_FSK2:inst12\|regs~clkctrl 3 COMB CLKCTRL_G1 3 " "Info: 3: + IC(0.808 ns) + CELL(0.000 ns) = 3.442 ns; Loc. = CLKCTRL_G1; Fanout = 3; COMB Node = 'PL_FSK2:inst12\|regs~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.808 ns" { PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.666 ns) 4.920 ns PL_FSK2:inst12\|cnt\[2\] 4 REG LCFF_X1_Y6_N3 2 " "Info: 4: + IC(0.812 ns) + CELL(0.666 ns) = 4.920 ns; Loc. = LCFF_X1_Y6_N3; Fanout = 2; REG Node = 'PL_FSK2:inst12\|cnt\[2\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.478 ns" { PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[2] } "NODE_NAME" } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 56.42 % ) " "Info: Total cell delay = 2.776 ns ( 56.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.144 ns ( 43.58 % ) " "Info: Total interconnect delay = 2.144 ns ( 43.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { clk PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.920 ns" { clk {} clk~combout {} PL_FSK2:inst12|regs {} PL_FSK2:inst12|regs~clkctrl {} PL_FSK2:inst12|cnt[2] {} } { 0.000ns 0.000ns 0.524ns 0.808ns 0.812ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.619 ns" { clk PL_FSK2:inst12|q[0] PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|B_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.619 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[0] {} PL_FSK2:inst12|Equal1~17 {} PL_FSK2:inst12|B_S {} } { 0.000ns 0.000ns 0.524ns 0.745ns 0.423ns } { 0.000ns 1.140ns 0.970ns 0.202ns 0.615ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { clk PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.920 ns" { clk {} clk~combout {} PL_FSK2:inst12|regs {} PL_FSK2:inst12|regs~clkctrl {} PL_FSK2:inst12|cnt[2] {} } { 0.000ns 0.000ns 0.524ns 0.808ns 0.812ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.613 ns + " "Info: + Micro setup delay of destination is 1.613 ns" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 35 -1 0 } } { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 11 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.649 ns" { PL_FSK2:inst12|cnt[2] PL_FSK2:inst12|B_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "0.649 ns" { PL_FSK2:inst12|cnt[2] {} PL_FSK2:inst12|B_S {} } { 0.000ns 0.443ns } { 0.000ns 0.206ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.619 ns" { clk PL_FSK2:inst12|q[0] PL_FSK2:inst12|Equal1~17 PL_FSK2:inst12|B_S } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.619 ns" { clk {} clk~combout {} PL_FSK2:inst12|q[0] {} PL_FSK2:inst12|Equal1~17 {} PL_FSK2:inst12|B_S {} } { 0.000ns 0.000ns 0.524ns 0.745ns 0.423ns } { 0.000ns 1.140ns 0.970ns 0.202ns 0.615ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { clk PL_FSK2:inst12|regs PL_FSK2:inst12|regs~clkctrl PL_FSK2:inst12|cnt[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.920 ns" { clk {} clk~combout {} PL_FSK2:inst12|regs {} PL_FSK2:inst12|regs~clkctrl {} PL_FSK2:inst12|cnt[2] {} } { 0.000ns 0.000ns 0.524ns 0.808ns 0.812ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}