fsk.hier_info

用vhdl写的fpga移频键控程序

|FSK
demodul_signal <= PL_FSK2:inst12.B_S
clk => PL_FSK2:inst12.clk
clk => PL_FSK:inst.clk
start2 => PL_FSK2:inst12.start
start1 => PL_FSK:inst.start
modul_signal => PL_FSK:inst.B_S


|FSK|PL_FSK2:inst12
clk => regs.CLK
clk => q[3].CLK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
start => q~7.OUTPUTSELECT
start => q~6.OUTPUTSELECT
start => q~5.OUTPUTSELECT
start => q~4.OUTPUTSELECT
M_S => regs.DATAIN
B_S <= B_S$latch.DB_MAX_OUTPUT_PORT_TYPE


|FSK|PL_FSK:inst
clk => q1[3].CLK
clk => q1[2].CLK
clk => q1[1].CLK
clk => q1[0].CLK
clk => f1.CLK
clk => q2[1].CLK
clk => q2[0].CLK
clk => f2.CLK
clk => M_S~reg0.CLK
start => q2~4.OUTPUTSELECT
start => q2~5.OUTPUTSELECT
start => q1~11.OUTPUTSELECT
start => q1~10.OUTPUTSELECT
start => q1~9.OUTPUTSELECT
start => q1~8.OUTPUTSELECT
start => f1.ENA
start => f2.ENA
B_S => M_S~0.OUTPUTSELECT
M_S <= M_S~reg0.DB_MAX_OUTPUT_PORT_TYPE