fsk.map.qmsg

用vhdl写的fpga移频键控程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 28 12:11:46 2008 " "Info: Processing started: Thu Feb 28 12:11:46 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FSK -c FSK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FSK -c FSK" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PL_FSK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PL_FSK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PL_FSK-behav " "Info: Found design unit 1: PL_FSK-behav" {  } { { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 PL_FSK " "Info: Found entity 1: PL_FSK" {  } { { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PL_FSK2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PL_FSK2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PL_FSK2-behav " "Info: Found design unit 1: PL_FSK2-behav" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 PL_FSK2 " "Info: Found entity 1: PL_FSK2" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSK.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FSK.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FSK " "Info: Found entity 1: FSK" {  } { { "FSK.bdf" "" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FSK " "Info: Elaborating entity \"FSK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PL_FSK2 PL_FSK2:inst12 " "Info: Elaborating entity \"PL_FSK2\" for hierarchy \"PL_FSK2:inst12\"" {  } { { "FSK.bdf" "inst12" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 72 360 456 168 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cnt PL_FSK2.vhd(38) " "Warning (10492): VHDL Process Statement warning at PL_FSK2.vhd(38): signal \"cnt\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 38 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "B_S PL_FSK2.vhd(33) " "Warning (10631): VHDL Process Statement warning at PL_FSK2.vhd(33): inferring latch(es) for signal or variable \"B_S\", which holds its previous value in one or more paths through the process" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 33 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "B_S PL_FSK2.vhd(33) " "Info (10041): Inferred latch for \"B_S\" at PL_FSK2.vhd(33)" {  } { { "PL_FSK2.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK2.vhd" 33 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PL_FSK PL_FSK:inst " "Info: Elaborating entity \"PL_FSK\" for hierarchy \"PL_FSK:inst\"" {  } { { "FSK.bdf" "inst" { Schematic "E:/My_Design/VHDL/FSK/FSK.bdf" { { 104 168 264 200 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PL_FSK:inst\|q2\[1\] data_in GND " "Warning (14130): Reduced register \"PL_FSK:inst\|q2\[1\]\" with stuck data_in port to stuck value GND" {  } { { "PL_FSK.vhd" "" { Text "E:/My_Design/VHDL/FSK/PL_FSK.vhd" 40 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "27 " "Info: Implemented 27 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "22 " "Info: Implemented 22 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 28 12:11:50 2008 " "Info: Processing ended: Thu Feb 28 12:11:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}