fsk.tan.rpt

用vhdl写的fpga移频键控程序

    Warning: Node "PL_FSK2:inst12|B_S" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "PL_FSK2:inst12|q[1]" as buffer
    Info: Detected ripple clock "PL_FSK2:inst12|q[0]" as buffer
    Info: Detected ripple clock "PL_FSK2:inst12|q[2]" as buffer
    Info: Detected ripple clock "PL_FSK2:inst12|q[3]" as buffer
    Info: Detected gated clock "PL_FSK2:inst12|Equal1~17" as buffer
    Info: Detected ripple clock "PL_FSK2:inst12|regs" as buffer
Info: Clock "clk" has Internal fmax of 174.4 MHz between source register "PL_FSK2:inst12|cnt[2]" and destination register "PL_FSK2:inst12|B_S" (period= 5.734 ns)
    Info: + Longest register to register delay is 0.649 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N3; Fanout = 2; REG Node = 'PL_FSK2:inst12|cnt[2]'
        Info: 2: + IC(0.443 ns) + CELL(0.206 ns) = 0.649 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12|B_S'
        Info: Total cell delay = 0.206 ns ( 31.74 % )
        Info: Total interconnect delay = 0.443 ns ( 68.26 % )
    Info: - Smallest clock skew is -0.301 ns
        Info: + Shortest clock path from clock "clk" to destination register is 4.619 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 6; REG Node = 'PL_FSK2:inst12|q[0]'
            Info: 3: + IC(0.745 ns) + CELL(0.202 ns) = 3.581 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 4; COMB Node = 'PL_FSK2:inst12|Equal1~17'
            Info: 4: + IC(0.423 ns) + CELL(0.615 ns) = 4.619 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12|B_S'
            Info: Total cell delay = 2.927 ns ( 63.37 % )
            Info: Total interconnect delay = 1.692 ns ( 36.63 % )
        Info: - Longest clock path from clock "clk" to source register is 4.920 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N17; Fanout = 1; REG Node = 'PL_FSK2:inst12|regs'
            Info: 3: + IC(0.808 ns) + CELL(0.000 ns) = 3.442 ns; Loc. = CLKCTRL_G1; Fanout = 3; COMB Node = 'PL_FSK2:inst12|regs~clkctrl'
            Info: 4: + IC(0.812 ns) + CELL(0.666 ns) = 4.920 ns; Loc. = LCFF_X1_Y6_N3; Fanout = 2; REG Node = 'PL_FSK2:inst12|cnt[2]'
            Info: Total cell delay = 2.776 ns ( 56.42 % )
            Info: Total interconnect delay = 2.144 ns ( 43.58 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is 1.613 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "PL_FSK2:inst12|q[0]" and destination pin or register "PL_FSK2:inst12|cnt[0]" for clock "clk" (Hold time is 465 ps)
    Info: + Largest clock skew is 2.590 ns
        Info: + Longest clock path from clock "clk" to destination register is 4.920 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N17; Fanout = 1; REG Node = 'PL_FSK2:inst12|regs'
            Info: 3: + IC(0.808 ns) + CELL(0.000 ns) = 3.442 ns; Loc. = CLKCTRL_G1; Fanout = 3; COMB Node = 'PL_FSK2:inst12|regs~clkctrl'
            Info: 4: + IC(0.812 ns) + CELL(0.666 ns) = 4.920 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 3; REG Node = 'PL_FSK2:inst12|cnt[0]'
            Info: Total cell delay = 2.776 ns ( 56.42 % )
            Info: Total interconnect delay = 2.144 ns ( 43.58 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.330 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.524 ns) + CELL(0.666 ns) = 2.330 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 6; REG Node = 'PL_FSK2:inst12|q[0]'
            Info: Total cell delay = 1.806 ns ( 77.51 % )
            Info: Total interconnect delay = 0.524 ns ( 22.49 % )
    Info: - Micro clock to output delay of source is 0.304 ns
    Info: - Shortest register to register delay is 2.127 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 6; REG Node = 'PL_FSK2:inst12|q[0]'
        Info: 2: + IC(0.745 ns) + CELL(0.202 ns) = 0.947 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 4; COMB Node = 'PL_FSK2:inst12|Equal1~17'
        Info: 3: + IC(0.421 ns) + CELL(0.651 ns) = 2.019 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 1; COMB Node = 'PL_FSK2:inst12|cnt[0]~152'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.127 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 3; REG Node = 'PL_FSK2:inst12|cnt[0]'
        Info: Total cell delay = 0.961 ns ( 45.18 % )
        Info: Total interconnect delay = 1.166 ns ( 54.82 % )
    Info: + Micro hold delay of destination is 0.306 ns
Info: tsu for register "PL_FSK:inst|f1" (data pin = "start1", clock pin = "clk") is 5.884 ns
    Info: + Longest pin to register delay is 8.684 ns
        Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_173; Fanout = 7; PIN Node = 'start1'
        Info: 2: + IC(6.865 ns) + CELL(0.855 ns) = 8.684 ns; Loc. = LCFF_X2_Y6_N13; Fanout = 1; REG Node = 'PL_FSK:inst|f1'
        Info: Total cell delay = 1.819 ns ( 20.95 % )
        Info: Total interconnect delay = 6.865 ns ( 79.05 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.760 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.811 ns) + CELL(0.666 ns) = 2.760 ns; Loc. = LCFF_X2_Y6_N13; Fanout = 1; REG Node = 'PL_FSK:inst|f1'
        Info: Total cell delay = 1.806 ns ( 65.43 % )
        Info: Total interconnect delay = 0.954 ns ( 34.57 % )
Info: tco from clock "clk" to destination pin "demodul_signal" through register "PL_FSK2:inst12|B_S" is 8.961 ns
    Info: + Longest clock path from clock "clk" to source register is 4.813 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.524 ns) + CELL(0.970 ns) = 2.634 ns; Loc. = LCFF_X1_Y6_N13; Fanout = 5; REG Node = 'PL_FSK2:inst12|q[1]'
        Info: 3: + IC(0.490 ns) + CELL(0.651 ns) = 3.775 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 4; COMB Node = 'PL_FSK2:inst12|Equal1~17'
        Info: 4: + IC(0.423 ns) + CELL(0.615 ns) = 4.813 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12|B_S'
        Info: Total cell delay = 3.376 ns ( 70.14 % )
        Info: Total interconnect delay = 1.437 ns ( 29.86 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.148 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; REG Node = 'PL_FSK2:inst12|B_S'
        Info: 2: + IC(1.052 ns) + CELL(3.096 ns) = 4.148 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'demodul_signal'
        Info: Total cell delay = 3.096 ns ( 74.64 % )
        Info: Total interconnect delay = 1.052 ns ( 25.36 % )
Info: th for register "PL_FSK:inst|M_S" (data pin = "modul_signal", clock pin = "clk") is -4.552 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.760 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.811 ns) + CELL(0.666 ns) = 2.760 ns; Loc. = LCFF_X2_Y6_N31; Fanout = 1; REG Node = 'PL_FSK:inst|M_S'
        Info: Total cell delay = 1.806 ns ( 65.43 % )
        Info: Total interconnect delay = 0.954 ns ( 34.57 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.618 ns
        Info: 1: + IC(0.000 ns) + CELL(0.975 ns) = 0.975 ns; Loc. = PIN_10; Fanout = 1; PIN Node = 'modul_signal'
        Info: 2: + IC(6.329 ns) + CELL(0.206 ns) = 7.510 ns; Loc. = LCCOMB_X2_Y6_N30; Fanout = 1; COMB Node = 'PL_FSK:inst|M_S~10'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.618 ns; Loc. = LCFF_X2_Y6_N31; Fanout = 1; REG Node = 'PL_FSK:inst|M_S'
        Info: Total cell delay = 1.289 ns ( 16.92 % )
        Info: Total interconnect delay = 6.329 ns ( 83.08 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Thu Feb 28 12:12:09 2008
    Info: Elapsed time: 00:00:02