fsk.tan.summary

用vhdl写的fpga移频键控程序

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.884 ns
From           : start1
To             : PL_FSK:inst|f2
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.961 ns
From           : PL_FSK2:inst12|B_S
To             : demodul_signal
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.552 ns
From           : modul_signal
To             : PL_FSK:inst|M_S
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 174.40 MHz ( period = 5.734 ns )
From           : PL_FSK2:inst12|cnt[2]
To             : PL_FSK2:inst12|B_S
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : PL_FSK2:inst12|q[0]
To             : PL_FSK2:inst12|cnt[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 12

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 12

--------------------------------------------------------------------------------------