fp64.vhd

用VHDL写的DS18B20温度采集程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp64 is
port(
     clk:in std_logic;
     clk64out:out std_logic
     );
end fp64;
architecture rtl of fp64 is
signal c:std_logic;
signal counter:integer range 5 downto 0;
begin
  process(clk)
    begin
     if rising_edge(clk) then
       if counter=5 then
          counter<=0;
          c<=not c;
       else counter<=counter+1;
       end if;
       clk64out<=c;
      end if;
  end process;
end rtl;