18b20.fit.rpt

用VHDL写的DS18B20温度采集程序

; Auto Merge PLLs                                ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs              ; Off                            ; Off                            ;
; Fitter Effort                                  ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                ; Normal                         ; Normal                         ;
; Auto Global Clock                              ; On                             ; On                             ;
; Auto Global Register Control Signals           ; On                             ; On                             ;
; Always Enable Input Buffers                    ; Off                            ; Off                            ;
+------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/VHDL典型电路设计/18b20/18b20.pin.


+---------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                             ;
+---------------------------------------------+-----------------------------+
; Resource                                    ; Usage                       ;
+---------------------------------------------+-----------------------------+
; Total logic elements                        ; 224 / 4,608 ( 5 % )         ;
;     -- Combinational with no register       ; 174                         ;
;     -- Register only                        ; 1                           ;
;     -- Combinational with a register        ; 49                          ;
;                                             ;                             ;
; Logic element usage by number of LUT inputs ;                             ;
;     -- 4 input functions                    ; 142                         ;
;     -- 3 input functions                    ; 39                          ;
;     -- <=2 input functions                  ; 42                          ;
;     -- Register only                        ; 1                           ;
;                                             ;                             ;
; Logic elements by mode                      ;                             ;
;     -- normal mode                          ; 205                         ;
;     -- arithmetic mode                      ; 18                          ;
;                                             ;                             ;
; Total registers                             ; 50 / 4,608 ( 1 % )          ;
; Total LABs                                  ; 18 / 288 ( 6 % )            ;
; User inserted logic elements                ; 0                           ;
; Virtual pins                                ; 0                           ;
; I/O pins                                    ; 3 / 142 ( 2 % )             ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )              ;
; Global signals                              ; 3                           ;
; M4Ks                                        ; 1 / 26 ( 4 % )              ;
; Total memory bits                           ; 1,216 / 119,808 ( 1 % )     ;
; Total RAM block bits                        ; 4,608 / 119,808 ( 4 % )     ;
; Embedded Multiplier 9-bit elements          ; 0 / 26 ( 0 % )              ;
; PLLs                                        ; 0 / 2 ( 0 % )               ;
; Global clocks                               ; 3 / 8 ( 38 % )              ;
; Maximum fan-out node                        ; fp64:inst7|clk64out~clkctrl ;
; Maximum fan-out                             ; 46                          ;
; Highest non-global fan-out signal           ; temp:inst|flag[1]           ;
; Highest non-global fan-out                  ; 45                          ;
; Total fan-out                               ; 901                         ;
; Average fan-out                             ; 3.17                        ;
+---------------------------------------------+-----------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk  ; 132   ; 3        ; 28           ; 7            ; 0           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                           ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; tout ; 89    ; 4        ; 19           ; 0            ; 0           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins                                                                                                                                                                                                                                                                                                                                       ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; mono_bus ; 90    ; 4        ; 21           ; 0            ; 3           ; 5                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; no              ; yes        ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; 0 pF ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 2 / 34 ( 6 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 35 ( 0 % ) ; 3.3V          ; --           ;
; 3        ; 2 / 37 ( 5 % ) ; 3.3V          ; --           ;
; 4        ; 2 / 36 ( 6 % ) ; 3.3V          ; --           ;
+----------+----------------+---------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                        ;
+----------+------------+----------+-------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1        ; 0          ; 1        ; +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; LVTTL        ;         ; Row I/O    ; N               ; no       ; Off          ;
; 2        ; 1          ; 1        ; +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; LVTTL        ;         ; Row I/O    ; N               ; no       ; Off          ;
; 3        ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 4        ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;