altpll0_waveforms.html

来自「用VHDL写的DS18B20温度采集程序」· HTML 代码 · 共 14 行

HTML

14 行

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<title>Sample Waveforms for altpll0.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file altpll0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design altpll0.vhd. The design altpll0.vhd has Cyclone II FAST pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 15625 ps. CLK0 multiply by = 1, CLK0 divide by = 64, CLK0 phase_shift = 0 Output port LOCKED is used. This port will go high when the PLL locks to the input clock. Input port ARESET is used. This port is active high. When asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. </P>
<CENTER><img src=altpll0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
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本页面展示了「用VHDL写的DS18B20温度采集程序」中的 altpll0_waveforms.html 源码文件，采用 HTML 编程语言编写，共 14 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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