18b20.map.rpt

用VHDL写的DS18B20温度采集程序

+--------------------------------------------+
; Source assignments for fp64:inst7          ;
+----------------+-------+------+------------+
; Assignment     ; Value ; From ; To         ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; High  ; -    ; counter[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; counter[1] ;
; POWER_UP_LEVEL ; High  ; -    ; counter[2] ;
+----------------+-------+------+------------+


+--------------------------------------------------------------------------------------+
; Source assignments for temp:inst|altsyncram:comb_rtl_0|altsyncram_g1v:auto_generated ;
+---------------------------------+--------------------+------+------------------------+
; Assignment                      ; Value              ; From ; To                     ;
+---------------------------------+--------------------+------+------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                      ;
+---------------------------------+--------------------+------+------------------------+


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: temp:inst|altsyncram:comb_rtl_0 ;
+------------------------------------+----------------+----------------------------+
; Parameter Name                     ; Value          ; Type                       ;
+------------------------------------+----------------+----------------------------+
; BYTE_SIZE_BLOCK                    ; 8              ; Untyped                    ;
; AUTO_CARRY_CHAINS                  ; ON             ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS               ; OFF            ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS                ; ON             ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS             ; OFF            ; IGNORE_CASCADE             ;
; OPERATION_MODE                     ; ROM            ; Untyped                    ;
; WIDTH_A                            ; 19             ; Untyped                    ;
; WIDTHAD_A                          ; 6              ; Untyped                    ;
; NUMWORDS_A                         ; 64             ; Untyped                    ;
; OUTDATA_REG_A                      ; UNREGISTERED   ; Untyped                    ;
; ADDRESS_ACLR_A                     ; NONE           ; Untyped                    ;
; OUTDATA_ACLR_A                     ; NONE           ; Untyped                    ;
; WRCONTROL_ACLR_A                   ; NONE           ; Untyped                    ;
; INDATA_ACLR_A                      ; NONE           ; Untyped                    ;
; BYTEENA_ACLR_A                     ; NONE           ; Untyped                    ;
; WIDTH_B                            ; 1              ; Untyped                    ;
; WIDTHAD_B                          ; 1              ; Untyped                    ;
; NUMWORDS_B                         ; 1              ; Untyped                    ;
; INDATA_REG_B                       ; CLOCK1         ; Untyped                    ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1         ; Untyped                    ;
; RDCONTROL_REG_B                    ; CLOCK1         ; Untyped                    ;
; ADDRESS_REG_B                      ; CLOCK1         ; Untyped                    ;
; OUTDATA_REG_B                      ; UNREGISTERED   ; Untyped                    ;
; BYTEENA_REG_B                      ; CLOCK1         ; Untyped                    ;
; INDATA_ACLR_B                      ; NONE           ; Untyped                    ;
; WRCONTROL_ACLR_B                   ; NONE           ; Untyped                    ;
; ADDRESS_ACLR_B                     ; NONE           ; Untyped                    ;
; OUTDATA_ACLR_B                     ; NONE           ; Untyped                    ;
; RDCONTROL_ACLR_B                   ; NONE           ; Untyped                    ;
; BYTEENA_ACLR_B                     ; NONE           ; Untyped                    ;
; WIDTH_BYTEENA_A                    ; 1              ; Untyped                    ;
; WIDTH_BYTEENA_B                    ; 1              ; Untyped                    ;
; RAM_BLOCK_TYPE                     ; AUTO           ; Untyped                    ;
; BYTE_SIZE                          ; 8              ; Untyped                    ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE      ; Untyped                    ;
; INIT_FILE                          ; 18b200.rtl.mif ; Untyped                    ;
; INIT_FILE_LAYOUT                   ; PORT_A         ; Untyped                    ;
; MAXIMUM_DEPTH                      ; 0              ; Untyped                    ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL         ; Untyped                    ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL         ; Untyped                    ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL         ; Untyped                    ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL         ; Untyped                    ;
; DEVICE_FAMILY                      ; Cyclone II     ; Untyped                    ;
; CBXI_PARAMETER                     ; altsyncram_g1v ; Untyped                    ;
+------------------------------------+----------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Sep 21 14:49:32 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 18b20 -c 18b20
Info: Found 1 design units, including 1 entities, in source file 18b20.bdf
    Info: Found entity 1: 18b20
Info: Found 2 design units, including 1 entities, in source file inst1.vhd
    Info: Found design unit 1: temp-init
    Info: Found entity 1: temp
Info: Found 2 design units, including 1 entities, in source file fp64.vhd
    Info: Found design unit 1: fp64-rtl
    Info: Found entity 1: fp64
Info: Elaborating entity "18b20" for the top level hierarchy
Info: Elaborating entity "temp" for hierarchy "temp:inst"
Warning (10036): Verilog HDL or VHDL warning at inst1.vhd(23): object "light" assigned a value but never read
Info: Elaborating entity "fp64" for hierarchy "fp64:inst7"
Warning: Reduced register "temp:inst|wireout~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "temp:inst|flag[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "temp:inst|flag[7]" with stuck data_in port to stuck value GND
Warning: Created node "temp:inst|comb~66" as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design.
Info: State machine "|18b20|temp:inst|state" contains 17 states
Info: Selected Auto state machine encoding method for state machine "|18b20|temp:inst|state"
Info: Encoding result for state machine "|18b20|temp:inst|state"
    Info: Completed encoding using 17 state bits
        Info: Encoded state bit "temp:inst|state.read3"
        Info: Encoded state bit "temp:inst|state.read2"
        Info: Encoded state bit "temp:inst|state.read1"
        Info: Encoded state bit "temp:inst|state.read0"
        Info: Encoded state bit "temp:inst|state.w01"
        Info: Encoded state bit "temp:inst|state.w00"
        Info: Encoded state bit "temp:inst|state.w1"
        Info: Encoded state bit "temp:inst|state.w0"
        Info: Encoded state bit "temp:inst|state.s7"
        Info: Encoded state bit "temp:inst|state.s6"
        Info: Encoded state bit "temp:inst|state.s5"
        Info: Encoded state bit "temp:inst|state.s4"
        Info: Encoded state bit "temp:inst|state.s3"
        Info: Encoded state bit "temp:inst|state.s2"
        Info: Encoded state bit "temp:inst|state.s1"
        Info: Encoded state bit "temp:inst|state.s0"
        Info: Encoded state bit "temp:inst|state.s00"
    Info: State "|18b20|temp:inst|state.s00" uses code string "00000000000000000"
    Info: State "|18b20|temp:inst|state.s0" uses code string "00000000000000011"
    Info: State "|18b20|temp:inst|state.s1" uses code string "00000000000000101"
    Info: State "|18b20|temp:inst|state.s2" uses code string "00000000000001001"
    Info: State "|18b20|temp:inst|state.s3" uses code string "00000000000010001"
    Info: State "|18b20|temp:inst|state.s4" uses code string "00000000000100001"
    Info: State "|18b20|temp:inst|state.s5" uses code string "00000000001000001"
    Info: State "|18b20|temp:inst|state.s6" uses code string "00000000010000001"
    Info: State "|18b20|temp:inst|state.s7" uses code string "00000000100000001"
    Info: State "|18b20|temp:inst|state.w0" uses code string "00000001000000001"
    Info: State "|18b20|temp:inst|state.w1" uses code string "00000010000000001"
    Info: State "|18b20|temp:inst|state.w00" uses code string "00000100000000001"
    Info: State "|18b20|temp:inst|state.w01" uses code string "00001000000000001"
    Info: State "|18b20|temp:inst|state.read0" uses code string "00010000000000001"
    Info: State "|18b20|temp:inst|state.read1" uses code string "00100000000000001"
    Info: State "|18b20|temp:inst|state.read2" uses code string "01000000000000001"
    Info: State "|18b20|temp:inst|state.read3" uses code string "10000000000000001"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=64, WIDTH_A=19) from the following design logic: "temp:inst|comb~66"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "temp:inst|altsyncram:comb_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_g1v.tdf
    Info: Found entity 1: altsyncram_g1v
Warning: Reduced register "temp:inst|state.s00" with stuck data_in port to stuck value VCC
Info: Implemented 252 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 230 logic cells
    Info: Implemented 19 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Fri Sep 21 14:49:43 2007
    Info: Elapsed time: 00:00:12