rd_ds.vhd

用VHDL写的DS18B20温度采集程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rd_ds is
port(
	clk  : in std_logic;
	rst  : in std_logic;
	wire : inout std_logic
	);
end rd_ds;

architecture behave of rd_ds is
type states is(s00,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,
				w0,w1,w00,w10,read0,read1,read2,
				read3,read4);
signal state : states;
signal cnt : std_logic_vector(15 downto 0);
signal st : std_logic_vector(7 downto 0);
begin
	process(rst,clk,wire)
	variable flag : std_logic_vector(7 downto 0);
	begin
		if rst = '0' then
			state <= s00;
			cnt <= "00000000";
		elsif rising_edge(clk) then
			case state is
				when s00 =>
					state <= s0;
				when s0 =>
					wire <= '0';
					state <= s1;
				when s1 =>
					if cnt(14)='1' then
					--delay 480us
						wire <= 'Z';
						state <= s2;
						cnt <= X"0000";
					else cnt=cnt+1;
					end if;
				when s2 =>
					if cnt(12)='1' then
					--delay 100us
						state <= s3;
						cnt <= X"0000";
					else 
						cnt = cnt+1;
					end if;
				when s3 =>
					if wire='0' then
						state <= s4;
					elsif wire = '1' then
						state <= s0;
					end if;
				when s4 =>
					if cnt(14)='1' then
					--delay 480us
						cnt <= X"0000";
						state <= s5;
					else 
						cnt <= cnt+1;
					end if;
				when s5 =>
					--write ds18b20 commod
					case st is
					--write 0xcc; skip rom
						when X"00" =>
							state <= w0;
							st <= X"01";
						when X"01" =>
							state <= w0;
							st <= X"02";
						when X"02" =>
							state <= w1;
							wire <= '0';
							st <= X"03";
						when X"03" =>
							state <= w1;
							wire <= '0';
							st <= X"04";
						when X"04" =>
							state <= w0;
							st <= X"05";
						when X"05" =>
							state <= w0;
							st <= X"06";
						when X"06" =>
							state <= w1;
							wire <= '0';
							st <= X"07";
						when X"07" =>
							state <= w1;
							wire <= '0';
							st <= X"08";
							
						--write 0x44; temperature convert
						when X"08" =>
							state <= w0;
							st <= X"09";
						when X"09" =>
							state <= w0;
							st <= X"0A";
						when X"0A" =>
							state <= w1;
							wire <= '0';
							st <= X"0B";
						when X"0B" =>
							state <= w0;
							st <= X"0C";
						when X"0C" =>
							state <= w0;
							st <= X"0D";
						when X"0D" =>
							state <= w0;
							st <= X"0E"";
						when X"0E" =>
							state <= w1;
							wire <= '0';
							st <= X"0F";
						when X"0F" =>
							state <= w0;
							st <= X"10";
							
						--write 0xcc; skip rom
						when X"10" =>
							state <= w0;
							st <= X"11";
						when X"11" =>
							state <= w0;
							st <= X"12";
						when X"12" =>
							state <= w1;
							wire <= '0';
							st <= X"13";
						when X"13" =>
							state <= w1;
							wire <= '0';
							st <= X"14";
						when X"14" =>
							state <= w0;
							st <= X"15";
						when X"15" =>
							state <= w0;
							st <= X"16";
						when X"16" =>
							state <= w1;
							wire <= '0';
							st <= X"17";
						when X"17" =>
							state <= w1;
							wire <= '0';
							st <= X"18";
							
						--write 0xbe;read register
						when X"18" =>
							state <= w0;
							st <= X"19";
						when X"19" =>
							state <= w1;
							wire <= '0';
							st <= X"1A";
						when X"1A" =>
							state <= w1;
							wire <= '0';
							st <= X"1B";
						when X"1B" =>
							state <= w1;
							wire <= '0';
							st <= X"1C";
						when X"1C" =>
							state <= w1;
							wire <= '0';
							st <= X"1D";
						when X"1D" =>
							state <= w1;
							wire <= '0';
							st <= X"1E";
						when X"1E" =>
							state <= w0;
							st <= X"1F";
						when X"1F" =>
							state <= w1;
							wire <= '0';
							st <= X"20";
							
						when X"20" =>
							st <= X"30";
							state <= s7;
							
				when s6 =>
					if (cnt(25)='1' or wite='1') then
					--delay 1s
						state <= s0;
						cnt <= X"0000";
					else
						cnt <= cnt+1;
					end if;
				
				--read data	
				when s7 =>
					case st is 
						when X"30" =>
							st <= X"31";
							state <= read0;
							wire <= '0';
						when X"31" =>
							st <= X"32";
							state <= read0;
							wire <= '0';
						when X"32" =>
							st <= X"33";
							state <= read0;
							wire <= '0';
						when X"33" =>
							st <= X"34";
							state <= read0;
							wire <= '0';
						when X"34" =>
							st <= X"35";
							state <= read0;
							wire <= '0';
						when X"35" =>
							st <= X"36";
							state <= read0;
							wire <= '0';
						when X"36" =>
							st <= X"37";
							state <= read0;
							wire <= '0';
						when X"37" =>
							st <= X"38";
							state <= read0;
							wire <= '0';
						when X"38" =>
							st <= X"39";
							state <= read0;
							wire <= '0';
						when X"39" =>
							st <= X"3A";
							state <= read0;
							wire <= '0';
						when X"3A" =>
							st <= X"3B";
							state <= read0;
							wire <= '0';
						when X"3B" =>
							st <= X"3C";
							state <= read0;
							wire <= '0';
						when X"3C" =>
							st <= X"3D";
							state <= read0;
							wire <= '0';
						when X"3D" =>
							st <= X"3E";
							state <= read0;
							wire <= '0';
						when X"3E" =>
							st <= X"3F";
							state <= read0;
							wire <= '0';
						when X"3F" =>
							st <= X"00";
							state <= s0
					end case;

				when w0 =>
					wire <= '0';
					if cnt(12)='1' then
					--delay 100us
						wire <= 'Z';
						cnt <= X"0000";
						state <= w00;
					else 
						cnt <= cnt+1;
					end if;
				when w00 =>
					state <= s5;
					
				when w1 =>
					state <= w10;
				when w10 =>
					wire <= 'Z';
					if cnt(12)='1' then
					--delay 100us
						cnt <= X"0000";
						state <= s5;
					else
						cnt <= cnt+1;
					end if;
					
				when read0 =>
					state <= read1;
				when read1 =>
					wire <= 'Z';
					if cnt(9)='1' then
					--delay 15us
						cnt <= X"0000";
						state <= read2;
					else 
						cnt <= cnt+1;
					end if;
				when read2 =>
					state <= read3;
				when read3 =>
					if cnt(11)='1' then
					--delay 60us
						cnt <= X"0000";
						state <= s7;
					else
						cnt <= cnt+1;
					end if;
				when others =>
					state <= s00;
			end case;
		end if;
	end process;