18b20.tan.summary

用VHDL写的DS18B20温度采集程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.632 ns
From           : mono_bus
To             : temp:inst|state.s7
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.061 ns
From           : temp:inst|wireout~en
To             : mono_bus
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.255 ns
From           : mono_bus
To             : temp:inst|led
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 103.77 MHz ( period = 9.637 ns )
From           : temp:inst|altsyncram:comb_rtl_0|altsyncram_g1v:auto_generated|ram_block1a0~porta_address_reg5
To             : temp:inst|altsyncram:comb_rtl_0|altsyncram_g1v:auto_generated|ram_block1a0~porta_address_reg5
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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