divclk.vhd

来自「ppm脉位调制数字基带系统的设计」· VHDL 代码 · 共 25 行

--function : bi div clock
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity divclk is
port(
	clk_in : in std_logic;
	clko1 : out std_logic;
	clko2 : out std_logic
	);
end divclk;

architecture behave of divclk is
signal cnt : std_logic_vector(4 downto 0);
begin
	process(clk_in)
	begin
		if clk_in'event and clk_in = '1' then
			cnt <= cnt + 1;
		end if;
	end process;
	clko1 <= cnt(0);
	clko2 <= cnt(1);
end behave;