ppm.map.qmsg

ppm脉位调制数字基带系统的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 01 12:34:11 2008 " "Info: Processing started: Sun Jun 01 12:34:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PPM -c PPM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PPM -c PPM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "S_to_P.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file S_to_P.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 S_to_P-behave " "Info: Found design unit 1: S_to_P-behave" {  } { { "S_to_P.vhd" "" { Text "F:/My_Design/FPGA/PPM/S_to_P.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 S_to_P " "Info: Found entity 1: S_to_P" {  } { { "S_to_P.vhd" "" { Text "F:/My_Design/FPGA/PPM/S_to_P.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divclk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divclk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divclk-behave " "Info: Found design unit 1: divclk-behave" {  } { { "divclk.vhd" "" { Text "F:/My_Design/FPGA/PPM/divclk.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divclk " "Info: Found entity 1: divclk" {  } { { "divclk.vhd" "" { Text "F:/My_Design/FPGA/PPM/divclk.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "compare.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file compare.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 compare-behave " "Info: Found design unit 1: compare-behave" {  } { { "compare.vhd" "" { Text "F:/My_Design/FPGA/PPM/compare.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 compare " "Info: Found entity 1: compare" {  } { { "compare.vhd" "" { Text "F:/My_Design/FPGA/PPM/compare.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "N_pulser.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file N_pulser.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 N_pulser-behave " "Info: Found design unit 1: N_pulser-behave" {  } { { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 N_pulser " "Info: Found entity 1: N_pulser" {  } { { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PPM.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file PPM.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PPM " "Info: Found entity 1: PPM" {  } { { "PPM.bdf" "" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PPM " "Info: Elaborating entity \"PPM\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "N_pulser N_pulser:inst3 " "Info: Elaborating entity \"N_pulser\" for hierarchy \"N_pulser:inst3\"" {  } { { "PPM.bdf" "inst3" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { { 72 496 592 168 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tmp N_pulser.vhd(24) " "Warning (10492): VHDL Process Statement warning at N_pulser.vhd(24): signal \"tmp\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s_dly N_pulser.vhd(25) " "Warning (10492): VHDL Process Statement warning at N_pulser.vhd(25): signal \"s_dly\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "compare compare:inst1 " "Info: Elaborating entity \"compare\" for hierarchy \"compare:inst1\"" {  } { { "PPM.bdf" "inst1" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { { 88 312 408 216 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tmp1 compare.vhd(24) " "Warning (10492): VHDL Process Statement warning at compare.vhd(24): signal \"tmp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "compare.vhd" "" { Text "F:/My_Design/FPGA/PPM/compare.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tmp2 compare.vhd(24) " "Warning (10492): VHDL Process Statement warning at compare.vhd(24): signal \"tmp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "compare.vhd" "" { Text "F:/My_Design/FPGA/PPM/compare.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tmp1 compare.vhd(25) " "Warning (10492): VHDL Process Statement warning at compare.vhd(25): signal \"tmp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "compare.vhd" "" { Text "F:/My_Design/FPGA/PPM/compare.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "S_to_P S_to_P:inst2 " "Info: Elaborating entity \"S_to_P\" for hierarchy \"S_to_P:inst2\"" {  } { { "PPM.bdf" "inst2" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { { 48 112 208 144 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divclk divclk:inst " "Info: Elaborating entity \"divclk\" for hierarchy \"divclk:inst\"" {  } { { "PPM.bdf" "inst" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { { 184 112 208 280 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "divclk:inst\|cnt\[2\] " "Info: Register \"divclk:inst\|cnt\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "divclk:inst\|cnt\[3\] " "Info: Register \"divclk:inst\|cnt\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "divclk:inst\|cnt\[4\] " "Info: Register \"divclk:inst\|cnt\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Allocated 155 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 01 12:34:15 2008 " "Info: Processing ended: Sun Jun 01 12:34:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}