ppm.tan.qmsg

ppm脉位调制数字基带系统的设计

{ "Info" "ITDB_TH_RESULT" "N_pulser:inst3\|tmp Data_in CLK -5.174 ns register " "Info: th for register \"N_pulser:inst3\|tmp\" (data pin = \"Data_in\", clock pin = \"CLK\") is -5.174 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.809 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PPM.bdf" "" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { { 208 -128 40 224 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 3 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "PPM.bdf" "" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { { 208 -128 40 224 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.809 ns N_pulser:inst3\|tmp 3 REG LCFF_X27_Y12_N19 1 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3\|tmp'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { CLK~clkctrl N_pulser:inst3|tmp } "NODE_NAME" } } { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.29 % ) " "Info: Total cell delay = 1.806 ns ( 64.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.003 ns ( 35.71 % ) " "Info: Total interconnect delay = 1.003 ns ( 35.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { CLK CLK~clkctrl N_pulser:inst3|tmp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { CLK {} CLK~combout {} CLK~clkctrl {} N_pulser:inst3|tmp {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.289 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns Data_in 1 PIN PIN_6 2 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 2; PIN Node = 'Data_in'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Data_in } "NODE_NAME" } } { "PPM.bdf" "" { Schematic "F:/My_Design/FPGA/PPM/PPM.bdf" { { 72 -128 40 88 "Data_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.561 ns) + CELL(0.615 ns) 8.181 ns N_pulser:inst3\|pulse~16 2 COMB LCCOMB_X27_Y12_N18 1 " "Info: 2: + IC(6.561 ns) + CELL(0.615 ns) = 8.181 ns; Loc. = LCCOMB_X27_Y12_N18; Fanout = 1; COMB Node = 'N_pulser:inst3\|pulse~16'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.176 ns" { Data_in N_pulser:inst3|pulse~16 } "NODE_NAME" } } { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.289 ns N_pulser:inst3\|tmp 3 REG LCFF_X27_Y12_N19 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.289 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3\|tmp'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { N_pulser:inst3|pulse~16 N_pulser:inst3|tmp } "NODE_NAME" } } { "N_pulser.vhd" "" { Text "F:/My_Design/FPGA/PPM/N_pulser.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.728 ns ( 20.85 % ) " "Info: Total cell delay = 1.728 ns ( 20.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.561 ns ( 79.15 % ) " "Info: Total interconnect delay = 6.561 ns ( 79.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.289 ns" { Data_in N_pulser:inst3|pulse~16 N_pulser:inst3|tmp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.289 ns" { Data_in {} Data_in~combout {} N_pulser:inst3|pulse~16 {} N_pulser:inst3|tmp {} } { 0.000ns 0.000ns 6.561ns 0.000ns } { 0.000ns 1.005ns 0.615ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { CLK CLK~clkctrl N_pulser:inst3|tmp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { CLK {} CLK~combout {} CLK~clkctrl {} N_pulser:inst3|tmp {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.289 ns" { Data_in N_pulser:inst3|pulse~16 N_pulser:inst3|tmp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.289 ns" { Data_in {} Data_in~combout {} N_pulser:inst3|pulse~16 {} N_pulser:inst3|tmp {} } { 0.000ns 0.000ns 6.561ns 0.000ns } { 0.000ns 1.005ns 0.615ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 01 12:34:28 2008 " "Info: Processing ended: Sun Jun 01 12:34:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}