n_pulser.vhd

来自「ppm脉位调制数字基带系统的设计」· VHDL 代码 · 共 41 行

--function : N_pulser.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity N_pulser is
port(
	clk : in std_logic;
	sin : in std_logic;
	pulse : out std_logic
	);
end N_pulser;

architecture behave of N_pulser is
signal tmp : std_logic;
signal s_dly : std_logic;
signal p_latch : std_logic;
begin
	lth1 : process(clk,sin)
	begin
		if clk'event and clk = '1' then
			tmp <= sin;
		end if;
		s_dly <= not tmp;
		pulse <= sin and s_dly;
	end process;

--	rst : process(s_dly,sin)
--	begin
--		pulse <= sin and s_dly;
--	end process;
	
--	lth2 : process(clk,p_latch)
--	begin
--		if clk'event and clk = '1' then
--			pulse <= p_latch;
--		else
--			pulse <= 'Z';
--		end if;
--	end process;
end behave;