ppm.tan.rpt

ppm脉位调制数字基带系统的设计

+-------+--------------+------------+--------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To      ; From Clock ;
+-------+--------------+------------+--------------------+---------+------------+
; N/A   ; None         ; 8.741 ns   ; divclk:inst|cnt[1] ; PPM_out ; CLK        ;
; N/A   ; None         ; 8.456 ns   ; divclk:inst|cnt[0] ; PPM_out ; CLK        ;
; N/A   ; None         ; 8.097 ns   ; N_pulser:inst3|tmp ; PPM_out ; CLK        ;
+-------+--------------+------------+--------------------+---------+------------+


+-----------------------------------------------------------------+
; tpd                                                             ;
+-------+-------------------+-----------------+---------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To      ;
+-------+-------------------+-----------------+---------+---------+
; N/A   ; None              ; 11.668 ns       ; Data_in ; PPM_out ;
+-------+-------------------+-----------------+---------+---------+


+-----------------------------------------------------------------------------------+
; th                                                                                ;
+---------------+-------------+-----------+---------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To                 ; To Clock ;
+---------------+-------------+-----------+---------+--------------------+----------+
; N/A           ; None        ; -5.174 ns ; Data_in ; N_pulser:inst3|tmp ; CLK      ;
+---------------+-------------+-----------+---------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Jun 01 12:34:27 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PPM -c PPM --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 340.02 MHz between source register "divclk:inst|cnt[0]" and destination register "N_pulser:inst3|tmp"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.092 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N3; Fanout = 4; REG Node = 'divclk:inst|cnt[0]'
            Info: 2: + IC(0.452 ns) + CELL(0.532 ns) = 0.984 ns; Loc. = LCCOMB_X27_Y12_N18; Fanout = 1; COMB Node = 'N_pulser:inst3|pulse~16'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.092 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3|tmp'
            Info: Total cell delay = 0.640 ns ( 58.61 % )
            Info: Total interconnect delay = 0.452 ns ( 41.39 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.809 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3|tmp'
                Info: Total cell delay = 1.806 ns ( 64.29 % )
                Info: Total interconnect delay = 1.003 ns ( 35.71 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.809 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N3; Fanout = 4; REG Node = 'divclk:inst|cnt[0]'
                Info: Total cell delay = 1.806 ns ( 64.29 % )
                Info: Total interconnect delay = 1.003 ns ( 35.71 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "N_pulser:inst3|tmp" (data pin = "Data_in", clock pin = "CLK") is 5.440 ns
    Info: + Longest pin to register delay is 8.289 ns
        Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 2; PIN Node = 'Data_in'
        Info: 2: + IC(6.561 ns) + CELL(0.615 ns) = 8.181 ns; Loc. = LCCOMB_X27_Y12_N18; Fanout = 1; COMB Node = 'N_pulser:inst3|pulse~16'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.289 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3|tmp'
        Info: Total cell delay = 1.728 ns ( 20.85 % )
        Info: Total interconnect delay = 6.561 ns ( 79.15 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.809 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3|tmp'
        Info: Total cell delay = 1.806 ns ( 64.29 % )
        Info: Total interconnect delay = 1.003 ns ( 35.71 % )
Info: tco from clock "CLK" to destination pin "PPM_out" through register "divclk:inst|cnt[1]" is 8.741 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.809 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N1; Fanout = 3; REG Node = 'divclk:inst|cnt[1]'
        Info: Total cell delay = 1.806 ns ( 64.29 % )
        Info: Total interconnect delay = 1.003 ns ( 35.71 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.628 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N1; Fanout = 3; REG Node = 'divclk:inst|cnt[1]'
        Info: 2: + IC(1.074 ns) + CELL(0.624 ns) = 1.698 ns; Loc. = LCCOMB_X27_Y12_N8; Fanout = 1; COMB Node = 'N_pulser:inst3|pulse~15'
        Info: 3: + IC(0.640 ns) + CELL(3.290 ns) = 5.628 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'PPM_out'
        Info: Total cell delay = 3.914 ns ( 69.55 % )
        Info: Total interconnect delay = 1.714 ns ( 30.45 % )
Info: Longest tpd from source pin "Data_in" to destination pin "PPM_out" is 11.668 ns
    Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 2; PIN Node = 'Data_in'
    Info: 2: + IC(6.527 ns) + CELL(0.206 ns) = 7.738 ns; Loc. = LCCOMB_X27_Y12_N8; Fanout = 1; COMB Node = 'N_pulser:inst3|pulse~15'
    Info: 3: + IC(0.640 ns) + CELL(3.290 ns) = 11.668 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'PPM_out'
    Info: Total cell delay = 4.501 ns ( 38.58 % )
    Info: Total interconnect delay = 7.167 ns ( 61.42 % )
Info: th for register "N_pulser:inst3|tmp" (data pin = "Data_in", clock pin = "CLK") is -5.174 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.809 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3|tmp'
        Info: Total cell delay = 1.806 ns ( 64.29 % )
        Info: Total interconnect delay = 1.003 ns ( 35.71 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 8.289 ns
        Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 2; PIN Node = 'Data_in'
        Info: 2: + IC(6.561 ns) + CELL(0.615 ns) = 8.181 ns; Loc. = LCCOMB_X27_Y12_N18; Fanout = 1; COMB Node = 'N_pulser:inst3|pulse~16'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.289 ns; Loc. = LCFF_X27_Y12_N19; Fanout = 1; REG Node = 'N_pulser:inst3|tmp'
        Info: Total cell delay = 1.728 ns ( 20.85 % )
        Info: Total interconnect delay = 6.561 ns ( 79.15 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 113 megabytes of memory during processing
    Info: Processing ended: Sun Jun 01 12:34:28 2008
    Info: Elapsed time: 00:00:01