ppm.map.rpt

ppm脉位调制数字基带系统的设计

+------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                       ;
+----------------------------------+-----------------+------------------------------------+------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path       ;
+----------------------------------+-----------------+------------------------------------+------------------------------------+
; S_to_P.vhd                       ; yes             ; User VHDL File                     ; F:/My_Design/FPGA/PPM/S_to_P.vhd   ;
; divclk.vhd                       ; yes             ; User VHDL File                     ; F:/My_Design/FPGA/PPM/divclk.vhd   ;
; compare.vhd                      ; yes             ; User VHDL File                     ; F:/My_Design/FPGA/PPM/compare.vhd  ;
; N_pulser.vhd                     ; yes             ; User VHDL File                     ; F:/My_Design/FPGA/PPM/N_pulser.vhd ;
; PPM.bdf                          ; yes             ; User Block Diagram/Schematic File  ; F:/My_Design/FPGA/PPM/PPM.bdf      ;
+----------------------------------+-----------------+------------------------------------+------------------------------------+


+------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                      ;
+---------------------------------------------+--------------------+
; Resource                                    ; Usage              ;
+---------------------------------------------+--------------------+
; Estimated Total logic elements              ; 4                  ;
;                                             ;                    ;
; Total combinational functions               ; 4                  ;
; Logic element usage by number of LUT inputs ;                    ;
;     -- 4 input functions                    ; 1                  ;
;     -- 3 input functions                    ; 1                  ;
;     -- <=2 input functions                  ; 2                  ;
;                                             ;                    ;
; Logic elements by mode                      ;                    ;
;     -- normal mode                          ; 4                  ;
;     -- arithmetic mode                      ; 0                  ;
;                                             ;                    ;
; Total registers                             ; 3                  ;
;     -- Dedicated logic registers            ; 3                  ;
;     -- I/O registers                        ; 0                  ;
;                                             ;                    ;
; I/O pins                                    ; 3                  ;
; Maximum fan-out node                        ; divclk:inst|cnt[0] ;
; Maximum fan-out                             ; 4                  ;
; Total fan-out                               ; 17                 ;
; Average fan-out                             ; 1.70               ;
+---------------------------------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |PPM                       ; 4 (0)             ; 3 (0)        ; 0           ; 0            ; 0       ; 0         ; 3    ; 0            ; |PPM                ; work         ;
;    |N_pulser:inst3|        ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PPM|N_pulser:inst3 ; work         ;
;    |divclk:inst|           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PPM|divclk:inst    ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; divclk:inst|cnt[2..4]                 ; Lost fanout        ;
; Total Number of Removed Registers = 3 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Jun 01 12:34:11 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PPM -c PPM
Info: Found 2 design units, including 1 entities, in source file S_to_P.vhd
    Info: Found design unit 1: S_to_P-behave
    Info: Found entity 1: S_to_P
Info: Found 2 design units, including 1 entities, in source file divclk.vhd
    Info: Found design unit 1: divclk-behave
    Info: Found entity 1: divclk
Info: Found 2 design units, including 1 entities, in source file compare.vhd
    Info: Found design unit 1: compare-behave
    Info: Found entity 1: compare
Info: Found 2 design units, including 1 entities, in source file N_pulser.vhd
    Info: Found design unit 1: N_pulser-behave
    Info: Found entity 1: N_pulser
Info: Found 1 design units, including 1 entities, in source file PPM.bdf
    Info: Found entity 1: PPM
Info: Elaborating entity "PPM" for the top level hierarchy
Info: Elaborating entity "N_pulser" for hierarchy "N_pulser:inst3"
Warning (10492): VHDL Process Statement warning at N_pulser.vhd(24): signal "tmp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at N_pulser.vhd(25): signal "s_dly" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "compare" for hierarchy "compare:inst1"
Warning (10492): VHDL Process Statement warning at compare.vhd(24): signal "tmp1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at compare.vhd(24): signal "tmp2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at compare.vhd(25): signal "tmp1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "S_to_P" for hierarchy "S_to_P:inst2"
Info: Elaborating entity "divclk" for hierarchy "divclk:inst"
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "divclk:inst|cnt[2]" lost all its fanouts during netlist optimizations.
    Info: Register "divclk:inst|cnt[3]" lost all its fanouts during netlist optimizations.
    Info: Register "divclk:inst|cnt[4]" lost all its fanouts during netlist optimizations.
Info: Implemented 7 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 155 megabytes of memory during processing
    Info: Processing ended: Sun Jun 01 12:34:15 2008
    Info: Elapsed time: 00:00:04