s_to_p.vhd

来自「ppm脉位调制数字基带系统的设计」· VHDL 代码 · 共 18 行

--Serial convert Parallel 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity S_to_P is
port(
	sin : in std_logic;
	so1 : out std_logic;
	so2 : out std_logic
	);
end S_to_P;

architecture behave of S_to_P is
begin
	so1 <= (sin or sin) and (sin nand sin);
	so2 <= not(sin nand sin);
end behave;