duolufuyong.rpt

本程序利用VHDL语言实现拔河游戏机的功能

        | | | | | | +----- LC19 ~337~1
        | | | | | | | +--- LC17 ~346~1
        | | | | | | | | +- LC23 ~355~1
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> - - - * - * - - - | - * | <-- ~322~1
LC20 -> - - - - * - - - - | - * | <-- ~328~1
LC19 -> - - * - - - * - - | - * | <-- ~337~1
LC17 -> - * - - - - - * - | - * | <-- ~346~1
LC23 -> * - - - - - - - * | - * | <-- ~355~1

Pin
4    -> * - - - - - - - * | - * | <-- a0
13   -> - * - - - - - * - | - * | <-- a1
12   -> - - * - - - * - - | - * | <-- a2
11   -> - - - * - * - - - | - * | <-- a3
9    -> * - - - - - - - * | - * | <-- b0
8    -> - * - - - - - * - | - * | <-- b1
7    -> - - * - - - * - - | - * | <-- b2
6    -> - - - - * - - - - | - * | <-- b3
14   -> * * * * * * * * * | - * | <-- sa
5    -> * * * * * * * * * | - * | <-- sb


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      e:\bahe\yima\duolufuyong.rpt
duolufuyong

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
b0       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
sa       : INPUT;
sb       : INPUT;

-- Node name is 'q0' 
-- Equation name is 'q0', location is LC025, type is output.
 q0      = LCELL( _EQ001 $  GND);
  _EQ001 =  b0 & !sa &  sb &  _X001
         #  a0 &  sa & !sb
         #  _LC023 &  _X001 &  _X002;
  _X001  = EXP( sa & !sb);
  _X002  = EXP(!sa &  sb);

-- Node name is 'q1' 
-- Equation name is 'q1', location is LC024, type is output.
 q1      = LCELL( _EQ002 $  GND);
  _EQ002 =  b1 & !sa &  sb &  _X001
         #  a1 &  sa & !sb
         #  _LC017 &  _X001 &  _X002;
  _X001  = EXP( sa & !sb);
  _X002  = EXP(!sa &  sb);

-- Node name is 'q2' 
-- Equation name is 'q2', location is LC022, type is output.
 q2      = LCELL( _EQ003 $  GND);
  _EQ003 =  b2 & !sa &  sb &  _X001
         #  a2 &  sa & !sb
         #  _LC019 &  _X001 &  _X002;
  _X001  = EXP( sa & !sb);
  _X002  = EXP(!sa &  sb);

-- Node name is 'q3' 
-- Equation name is 'q3', location is LC018, type is output.
 q3      = LCELL( _EQ004 $  GND);
  _EQ004 =  a3 &  sa & !sb
         #  _LC021 &  _X001;
  _X001  = EXP( sa & !sb);

-- Node name is '~322~1' 
-- Equation name is '~322~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ005 $  _LC020);
  _EQ005 =  b3 & !_LC020 & !sa &  sb
         # !b3 &  _LC020 & !sa &  sb;

-- Node name is '~328~1' 
-- Equation name is '~328~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ006 $  _LC021);
  _EQ006 =  a3 & !_LC021 &  sa & !sb
         # !a3 &  _LC021 &  sa & !sb;

-- Node name is '~337~1' 
-- Equation name is '~337~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ007 $  GND);
  _EQ007 =  b2 & !sa &  sb &  _X001
         #  a2 &  sa & !sb
         #  _LC019 &  _X001 &  _X002;
  _X001  = EXP( sa & !sb);
  _X002  = EXP(!sa &  sb);

-- Node name is '~346~1' 
-- Equation name is '~346~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ008 $  GND);
  _EQ008 =  b1 & !sa &  sb &  _X001
         #  a1 &  sa & !sb
         #  _LC017 &  _X001 &  _X002;
  _X001  = EXP( sa & !sb);
  _X002  = EXP(!sa &  sb);

-- Node name is '~355~1' 
-- Equation name is '~355~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ009 $  GND);
  _EQ009 =  b0 & !sa &  sb &  _X001
         #  a0 &  sa & !sb
         #  _LC023 &  _X001 &  _X002;
  _X001  = EXP( sa & !sb);
  _X002  = EXP(!sa &  sb);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                               e:\bahe\yima\duolufuyong.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,861K