📄 baheyouxiji.rpt
字号:
_LC8_E14 = DFFE(!_LC8_E14, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is '|xianshi:g1|jishu2:d1|~4~1' = '|xianshi:g1|jishu2:d1|count~1'
-- Equation name is '_LC6_B10', type is buried
-- synthesized logic cell
_LC6_B10 = DFFE(!_LC6_B10, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is '|xianshi:g1|jishu10:k1|:11' = '|xianshi:g1|jishu10:k1|count0'
-- Equation name is '_LC2_E17', type is buried
_LC2_E17 = DFFE( _EQ035, q14, !clearxianshi, VCC, VCC);
_EQ035 = !bego & _LC2_E17
# bego & !_LC2_E17;
-- Node name is '|xianshi:g1|jishu10:k1|:10' = '|xianshi:g1|jishu10:k1|count1'
-- Equation name is '_LC5_E17', type is buried
_LC5_E17 = DFFE( _EQ036, q14, !clearxianshi, VCC, VCC);
_EQ036 = !_LC2_E17 & _LC5_E17 & _LC6_E17
# _LC2_E17 & !_LC5_E17 & _LC6_E17
# !bego & _LC5_E17;
-- Node name is '|xianshi:g1|jishu10:k1|:9' = '|xianshi:g1|jishu10:k1|count2'
-- Equation name is '_LC4_E17', type is buried
_LC4_E17 = DFFE( _EQ037, q14, !clearxianshi, VCC, VCC);
_EQ037 = _LC4_E17 & _LC6_E17 & !_LC7_E17
# !_LC4_E17 & _LC6_E17 & _LC7_E17
# !bego & _LC4_E17;
-- Node name is '|xianshi:g1|jishu10:k1|:8' = '|xianshi:g1|jishu10:k1|count3'
-- Equation name is '_LC8_E17', type is buried
_LC8_E17 = DFFE( _EQ038, q14, !clearxianshi, VCC, VCC);
_EQ038 = !_LC1_E17 & _LC6_E17 & _LC8_E17
# _LC1_E17 & _LC6_E17 & !_LC8_E17
# !bego & _LC8_E17;
-- Node name is '|xianshi:g1|jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_E17', type is buried
_LC7_E17 = LCELL( _EQ039);
_EQ039 = _LC2_E17 & _LC5_E17;
-- Node name is '|xianshi:g1|jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_E17', type is buried
_LC1_E17 = LCELL( _EQ040);
_EQ040 = _LC2_E17 & _LC4_E17 & _LC5_E17;
-- Node name is '|xianshi:g1|jishu10:k1|~63~1'
-- Equation name is '_LC3_E17', type is buried
-- synthesized logic cell
_LC3_E17 = LCELL( _EQ041);
_EQ041 = _LC4_E17
# _LC5_E17
# !_LC8_E17;
-- Node name is '|xianshi:g1|jishu10:k1|~141~1'
-- Equation name is '_LC6_E17', type is buried
-- synthesized logic cell
_LC6_E17 = LCELL( _EQ042);
_EQ042 = bego & !_LC2_E17
# bego & _LC3_E17;
-- Node name is '|xianshi:g1|jishu10:k2|:11' = '|xianshi:g1|jishu10:k2|count0'
-- Equation name is '_LC8_E20', type is buried
_LC8_E20 = DFFE( _EQ043, q0, !clearxianshi, VCC, VCC);
_EQ043 = !bego & _LC8_E20
# bego & !_LC8_E20;
-- Node name is '|xianshi:g1|jishu10:k2|:10' = '|xianshi:g1|jishu10:k2|count1'
-- Equation name is '_LC2_E20', type is buried
_LC2_E20 = DFFE( _EQ044, q0, !clearxianshi, VCC, VCC);
_EQ044 = _LC2_E20 & _LC6_E20 & !_LC8_E20
# !_LC2_E20 & _LC6_E20 & _LC8_E20
# !bego & _LC2_E20;
-- Node name is '|xianshi:g1|jishu10:k2|:9' = '|xianshi:g1|jishu10:k2|count2'
-- Equation name is '_LC1_E20', type is buried
_LC1_E20 = DFFE( _EQ045, q0, !clearxianshi, VCC, VCC);
_EQ045 = _LC1_E20 & _LC6_E20 & !_LC7_E20
# !_LC1_E20 & _LC6_E20 & _LC7_E20
# !bego & _LC1_E20;
-- Node name is '|xianshi:g1|jishu10:k2|:8' = '|xianshi:g1|jishu10:k2|count3'
-- Equation name is '_LC3_E20', type is buried
_LC3_E20 = DFFE( _EQ046, q0, !clearxianshi, VCC, VCC);
_EQ046 = _LC3_E20 & !_LC4_E20 & _LC6_E20
# !_LC3_E20 & _LC4_E20 & _LC6_E20
# !bego & _LC3_E20;
-- Node name is '|xianshi:g1|jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_E20', type is buried
_LC7_E20 = LCELL( _EQ047);
_EQ047 = _LC2_E20 & _LC8_E20;
-- Node name is '|xianshi:g1|jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_E20', type is buried
_LC4_E20 = LCELL( _EQ048);
_EQ048 = _LC1_E20 & _LC2_E20 & _LC8_E20;
-- Node name is '|xianshi:g1|jishu10:k2|~63~1'
-- Equation name is '_LC5_E20', type is buried
-- synthesized logic cell
_LC5_E20 = LCELL( _EQ049);
_EQ049 = _LC1_E20
# _LC2_E20
# !_LC3_E20;
-- Node name is '|xianshi:g1|jishu10:k2|~141~1'
-- Equation name is '_LC6_E20', type is buried
-- synthesized logic cell
_LC6_E20 = LCELL( _EQ050);
_EQ050 = bego & !_LC8_E20
# bego & _LC5_E20;
-- Node name is '|xianshi:g1|qiduanyima:g1|:324'
-- Equation name is '_LC7_E14', type is buried
!_LC7_E14 = _LC7_E14~NOT;
_LC7_E14~NOT = LCELL( _EQ051);
_EQ051 = _LC5_E14
# _LC4_E14
# _LC3_E14
# !_LC2_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:348'
-- Equation name is '_LC4_E16', type is buried
!_LC4_E16 = _LC4_E16~NOT;
_LC4_E16~NOT = LCELL( _EQ052);
_EQ052 = _LC5_E14
# _LC4_E14
# !_LC3_E14
# _LC2_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:360'
-- Equation name is '_LC2_E18', type is buried
!_LC2_E18 = _LC2_E18~NOT;
_LC2_E18~NOT = LCELL( _EQ053);
_EQ053 = !_LC5_E14
# _LC4_E14
# _LC3_E14
# _LC2_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:372'
-- Equation name is '_LC3_E18', type is buried
_LC3_E18 = LCELL( _EQ054);
_EQ054 = !_LC2_E14 & !_LC3_E14 & !_LC4_E14 & !_LC5_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:377'
-- Equation name is '_LC6_E18', type is buried
_LC6_E18 = LCELL( _EQ055);
_EQ055 = !_LC2_E14 & _LC3_E14
# _LC2_E14 & !_LC3_E14
# _LC4_E14
# _LC3_E14 & !_LC5_E14
# _LC2_E14 & !_LC5_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:408'
-- Equation name is '_LC7_E18', type is buried
_LC7_E18 = LCELL( _EQ056);
_EQ056 = _LC5_E18
# _LC3_E18;
-- Node name is '|xianshi:g1|qiduanyima:g1|:410'
-- Equation name is '_LC5_E18', type is buried
!_LC5_E18 = _LC5_E18~NOT;
_LC5_E18~NOT = LCELL( _EQ057);
_EQ057 = !_LC2_E14 & _LC3_E14 & !_LC4_E14
# !_LC2_E14 & !_LC4_E14 & _LC5_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|~441~1'
-- Equation name is '_LC8_E18', type is buried
-- synthesized logic cell
_LC8_E18 = LCELL( _EQ058);
_EQ058 = _LC3_E14 & _LC4_E14
# _LC2_E14 & _LC4_E14
# _LC3_E14 & !_LC5_E14
# !_LC2_E14 & !_LC5_E14
# _LC4_E14 & !_LC5_E14
# !_LC2_E14 & !_LC3_E14 & !_LC4_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:441'
-- Equation name is '_LC4_E18', type is buried
_LC4_E18 = LCELL( _EQ059);
_EQ059 = !_LC2_E18 & _LC8_E18
# _LC3_E18;
-- Node name is '|xianshi:g1|qiduanyima:g1|:474'
-- Equation name is '_LC1_E16', type is buried
_LC1_E16 = LCELL( _EQ060);
_EQ060 = _LC4_E14
# _LC3_E14 & !_LC5_E14
# !_LC2_E14 & !_LC5_E14
# !_LC2_E14 & _LC3_E14
# _LC2_E14 & !_LC3_E14 & _LC5_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:530'
-- Equation name is '_LC1_E18', type is buried
_LC1_E18 = LCELL( _EQ061);
_EQ061 = _LC4_E14
# !_LC2_E14
# !_LC3_E14 & !_LC5_E14
# _LC3_E14 & _LC5_E14;
-- Node name is '|xianshi:g1|qiduanyima:g1|:540'
-- Equation name is '_LC1_E14', type is buried
_LC1_E14 = LCELL( _EQ062);
_EQ062 = !_LC5_E18
# _LC1_E18
# _LC7_E14
# _LC3_E18;
-- Node name is '|xianshi:g1|qiduanyima:g1|:573'
-- Equation name is '_LC6_E14', type is buried
_LC6_E14 = LCELL( _EQ063);
_EQ063 = _LC3_E18
# !_LC2_E18 & !_LC7_E14;
Project Information d:\20050820113\bahe1\baheyouxiji.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,794K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -