📄 baheyouxiji.rpt
字号:
E: 0 2 0 0 8 0 0 0 0 7 0 0 0 1 8 0 2 8 8 8 8 8 0 0 5 73/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 2 0 0 8 0 0 0 0 8 0 0 0 1 8 0 2 8 8 8 8 8 0 0 5 74/0
Device-Specific Information: d:\20050820113\bahe1\baheyouxiji.rpt
baheyouxiji
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - E -- INPUT 0 0 0 13 bego
87 - - E -- INPUT 0 0 0 4 clearhexin
88 - - D -- INPUT 0 0 0 8 clearxianshi
125 - - - -- INPUT G 0 0 0 0 clk1
122 - - - 13 INPUT 0 0 0 10 cp
59 - - - 12 INPUT 0 0 0 1 left
21 - - D -- BIDIR 0 1 0 5 q0
22 - - D -- BIDIR 0 1 0 0 q1
23 - - D -- BIDIR 0 1 0 0 q2
26 - - E -- BIDIR 0 1 0 0 q3
27 - - E -- BIDIR 0 1 0 0 q4
28 - - E -- BIDIR 0 1 0 0 q5
29 - - E -- BIDIR 0 1 0 0 q6
30 - - F -- BIDIR 0 1 0 0 q7
31 - - F -- BIDIR 0 1 0 0 q8
32 - - F -- BIDIR 0 1 0 0 q9
33 - - F -- BIDIR 0 1 0 0 q10
36 - - - 24 BIDIR 0 1 0 0 q11
37 - - - 23 BIDIR 0 1 0 0 q12
38 - - - 22 BIDIR 0 1 0 0 q13
39 - - - 21 BIDIR 0 1 0 5 q14
70 - - - 05 INPUT 0 0 0 1 right
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\20050820113\bahe1\baheyouxiji.rpt
baheyouxiji
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
42 - - - 19 OUTPUT 0 0 0 0 jiedi
21 - - D -- TRI 0 1 0 5 q0
22 - - D -- TRI 0 1 0 0 q1
23 - - D -- TRI 0 1 0 0 q2
26 - - E -- TRI 0 1 0 0 q3
27 - - E -- TRI 0 1 0 0 q4
28 - - E -- TRI 0 1 0 0 q5
29 - - E -- TRI 0 1 0 0 q6
30 - - F -- TRI 0 1 0 0 q7
31 - - F -- TRI 0 1 0 0 q8
32 - - F -- TRI 0 1 0 0 q9
33 - - F -- TRI 0 1 0 0 q10
36 - - - 24 TRI 0 1 0 0 q11
37 - - - 23 TRI 0 1 0 0 q12
38 - - - 22 TRI 0 1 0 0 q13
39 - - - 21 TRI 0 1 0 5 q14
8 - - A -- OUTPUT 0 1 0 0 yy
51 - - - 14 OUTPUT 0 1 0 0 y0
49 - - - 14 OUTPUT 0 1 0 0 y1
48 - - - 15 OUTPUT 0 1 0 0 y2
47 - - - 16 OUTPUT 0 1 0 0 y3
46 - - - 17 OUTPUT 0 1 0 0 y4
44 - - - 18 OUTPUT 0 1 0 0 y5
43 - - - 18 OUTPUT 0 1 0 0 y6
96 - - B -- OUTPUT 0 1 0 0 zz
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\20050820113\bahe1\baheyouxiji.rpt
baheyouxiji
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - E 24 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:773
- 3 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:785
- 1 - E 19 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:797
- 7 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:809
- 6 - E 24 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:821
- 5 - E 19 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:833
- 1 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:845
- 4 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:857
- 3 - E 24 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:869
- 1 - E 24 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:881
- 6 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:893
- 5 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:905
- 2 - E 24 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:917
- 2 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:929
- 8 - E 21 AND2 0 4 1 0 |bahe:u1|hexin:p1|yima:g1|:1318
- 7 - E 05 DFFE 1 3 0 1 |bahe:u1|hexin:p1|zonghejishu:u1|dchufa:i1|:3
- 7 - E 19 AND2 0 3 0 1 |bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:58|addcore:adder|:59
- 8 - E 19 OR2 0 3 0 1 |bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|pcarry2
- 6 - E 19 DFFE 1 4 0 15 |bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|temp3 (|bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|:8)
- 2 - E 19 DFFE 1 4 0 17 |bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|temp2 (|bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|:9)
- 4 - E 19 DFFE 1 3 0 18 |bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|temp1 (|bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|:10)
- 3 - E 19 DFFE 1 1 0 19 |bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|temp0 (|bahe:u1|hexin:p1|zonghejishu:u1|jishu16:g1|:11)
- 8 - E 05 DFFE 1 3 0 3 |bahe:u1|hexin:p1|zonghejishu:u1|jkslect:u1|jout (|bahe:u1|hexin:p1|zonghejishu:u1|jkslect:u1|:5)
- 1 - E 13 AND2 s 1 2 0 3 |bahe:u1|hexin:p1|zonghejishu:u1|~67~1
- 2 - E 05 OR2 0 4 0 4 |bahe:u1|hexin:p1|zonghejishu:u1|:73
- 4 - E 02 DFFE 2 0 0 3 |bahe:u1|jicunqi:g1|dchufa:u1|:3
- 1 - E 02 DFFE 1 1 0 3 |bahe:u1|jicunqi:g1|dchufa:u2|:3
- 1 - E 05 DFFE 1 1 0 3 |bahe:u1|jicunqi:g1|dchufa:u3|:3
- 3 - E 05 DFFE 1 1 0 2 |bahe:u1|jicunqi:g1|dchufa:u4|:3
- 5 - E 05 AND2 0 4 0 1 |bahe:u1|jicunqi:g1|:60
- 4 - E 05 OR2 ! 0 4 0 1 |bahe:u1|jicunqi:g1|:69
- 6 - E 05 OR2 1 2 0 3 |bahe:u1|jicunqi:g1|:112
- 1 - E 10 DFFE 2 0 0 3 |bahe:u1|jicunqi:g2|dchufa:u1|:3
- 3 - E 10 DFFE 1 1 0 3 |bahe:u1|jicunqi:g2|dchufa:u2|:3
- 4 - E 10 DFFE 1 1 0 3 |bahe:u1|jicunqi:g2|dchufa:u3|:3
- 5 - E 10 DFFE 1 1 0 2 |bahe:u1|jicunqi:g2|dchufa:u4|:3
- 7 - E 10 AND2 0 4 0 1 |bahe:u1|jicunqi:g2|:60
- 6 - E 10 OR2 ! 0 4 0 1 |bahe:u1|jicunqi:g2|:69
- 2 - E 10 OR2 1 2 0 3 |bahe:u1|jicunqi:g2|:112
- 4 - E 14 OR2 0 3 0 9 |xianshi:g1|duolufuyong:w1|:328
- 2 - E 14 OR2 0 3 0 9 |xianshi:g1|duolufuyong:w1|:337
- 3 - E 14 OR2 0 3 0 9 |xianshi:g1|duolufuyong:w1|:346
- 5 - E 14 OR2 0 3 0 9 |xianshi:g1|duolufuyong:w1|:355
- 6 - B 10 DFFE +s 0 0 1 0 |xianshi:g1|jishu2:d1|count~1 (|xianshi:g1|jishu2:d1|~4~1)
- 8 - E 14 DFFE + 0 0 1 4 |xianshi:g1|jishu2:d1|count (|xianshi:g1|jishu2:d1|:4)
- 7 - E 17 AND2 0 2 0 1 |xianshi:g1|jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:55
- 1 - E 17 AND2 0 3 0 1 |xianshi:g1|jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:59
- 8 - E 17 DFFE 2 3 0 2 |xianshi:g1|jishu10:k1|count3 (|xianshi:g1|jishu10:k1|:8)
- 4 - E 17 DFFE 2 3 0 3 |xianshi:g1|jishu10:k1|count2 (|xianshi:g1|jishu10:k1|:9)
- 5 - E 17 DFFE 2 3 0 4 |xianshi:g1|jishu10:k1|count1 (|xianshi:g1|jishu10:k1|:10)
- 2 - E 17 DFFE 2 1 0 5 |xianshi:g1|jishu10:k1|count0 (|xianshi:g1|jishu10:k1|:11)
- 3 - E 17 OR2 s 0 3 0 1 |xianshi:g1|jishu10:k1|~63~1
- 6 - E 17 OR2 s 1 2 0 3 |xianshi:g1|jishu10:k1|~141~1
- 7 - E 20 AND2 0 2 0 1 |xianshi:g1|jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:55
- 4 - E 20 AND2 0 3 0 1 |xianshi:g1|jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:59
- 3 - E 20 DFFE 2 3 0 2 |xianshi:g1|jishu10:k2|count3 (|xianshi:g1|jishu10:k2|:8)
- 1 - E 20 DFFE 2 3 0 3 |xianshi:g1|jishu10:k2|count2 (|xianshi:g1|jishu10:k2|:9)
- 2 - E 20 DFFE 2 3 0 4 |xianshi:g1|jishu10:k2|count1 (|xianshi:g1|jishu10:k2|:10)
- 8 - E 20 DFFE 2 1 0 5 |xianshi:g1|jishu10:k2|count0 (|xianshi:g1|jishu10:k2|:11)
- 5 - E 20 OR2 s 0 3 0 1 |xianshi:g1|jishu10:k2|~63~1
- 6 - E 20 OR2 s 1 2 0 3 |xianshi:g1|jishu10:k2|~141~1
- 7 - E 14 OR2 ! 0 4 0 2 |xianshi:g1|qiduanyima:g1|:324
- 4 - E 16 OR2 ! 0 4 1 0 |xianshi:g1|qiduanyima:g1|:348
- 2 - E 18 OR2 ! 0 4 0 2 |xianshi:g1|qiduanyima:g1|:360
- 3 - E 18 AND2 0 4 0 4 |xianshi:g1|qiduanyima:g1|:372
- 6 - E 18 OR2 0 4 1 0 |xianshi:g1|qiduanyima:g1|:377
- 7 - E 18 OR2 0 2 1 0 |xianshi:g1|qiduanyima:g1|:408
- 5 - E 18 OR2 ! 0 4 0 2 |xianshi:g1|qiduanyima:g1|:410
- 8 - E 18 OR2 s 0 4 0 1 |xianshi:g1|qiduanyima:g1|~441~1
- 4 - E 18 OR2 0 3 1 0 |xianshi:g1|qiduanyima:g1|:441
- 1 - E 16 OR2 0 4 1 0 |xianshi:g1|qiduanyima:g1|:474
- 1 - E 18 OR2 0 4 0 1 |xianshi:g1|qiduanyima:g1|:530
- 1 - E 14 OR2 0 4 1 0 |xianshi:g1|qiduanyima:g1|:540
- 6 - E 14 OR2 0 3 1 0 |xianshi:g1|qiduanyima:g1|:573
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\20050820113\bahe1\baheyouxiji.rpt
baheyouxiji
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 2/ 96( 2%) 0/ 48( 0%) 3/ 48( 6%) 1/16( 6%) 0/16( 0%) 3/16( 18%)
E: 13/ 96( 13%) 5/ 48( 10%) 21/ 48( 43%) 2/16( 12%) 0/16( 0%) 4/16( 25%)
F: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 0/16( 0%) 4/16( 25%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 6/24( 25%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\20050820113\bahe1\baheyouxiji.rpt
baheyouxiji
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 cp
INPUT 5 q0
INPUT 5 q14
LCELL 4 |bahe:u1|hexin:p1|zonghejishu:u1|:73
INPUT 2 clk1
Device-Specific Information: d:\20050820113\bahe1\baheyouxiji.rpt
baheyouxiji
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clearxianshi
INPUT 4 clearhexin
Device-Specific Information: d:\20050820113\bahe1\baheyouxiji.rpt
baheyouxiji
** EQUATIONS **
bego : INPUT;
clearhexin : INPUT;
clearxianshi : INPUT;
clk1 : INPUT;
cp : INPUT;
left : INPUT;
right : INPUT;
-- Node name is 'jiedi'
-- Equation name is 'jiedi', type is output
jiedi = GND;
-- Node name is 'q0'
-- Equation name is 'q0', type is bidir
q0 = TRI(_LC5_E19, VCC);
-- Node name is 'q1'
-- Equation name is 'q1', type is bidir
q1 = TRI(_LC6_E24, VCC);
-- Node name is 'q2'
-- Equation name is 'q2', type is bidir
q2 = TRI(_LC7_E21, VCC);
-- Node name is 'q3'
-- Equation name is 'q3', type is bidir
q3 = TRI(_LC1_E19, VCC);
-- Node name is 'q4'
-- Equation name is 'q4', type is bidir
q4 = TRI(_LC3_E21, VCC);
-- Node name is 'q5'
-- Equation name is 'q5', type is bidir
q5 = TRI(_LC8_E24, VCC);
-- Node name is 'q6'
-- Equation name is 'q6', type is bidir
q6 = TRI(_LC8_E21, VCC);
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