📄 qiduanyima.rpt
字号:
- 1 - E 13 OR2 0 4 1 0 :540
- 4 - E 13 OR2 0 3 1 0 :573
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\bahe\qiduanyima.rpt
qiduanyima
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 7/ 48( 14%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\bahe\qiduanyima.rpt
qiduanyima
** EQUATIONS **
a : INPUT;
b : INPUT;
c : INPUT;
d : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC4_E13;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC1_E13;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = !_LC4_E16;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC2_E16;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC7_E17;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC3_E17;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC2_E17;
-- Node name is ':324'
-- Equation name is '_LC4_E17', type is buried
!_LC4_E17 = _LC4_E17~NOT;
_LC4_E17~NOT = LCELL( _EQ001);
_EQ001 = d
# a
# b
# !c;
-- Node name is ':348'
-- Equation name is '_LC4_E16', type is buried
!_LC4_E16 = _LC4_E16~NOT;
_LC4_E16~NOT = LCELL( _EQ002);
_EQ002 = d
# a
# !b
# c;
-- Node name is ':360'
-- Equation name is '_LC5_E17', type is buried
!_LC5_E17 = _LC5_E17~NOT;
_LC5_E17~NOT = LCELL( _EQ003);
_EQ003 = d
# !a
# b
# c;
-- Node name is ':372'
-- Equation name is '_LC1_E17', type is buried
_LC1_E17 = LCELL( _EQ004);
_EQ004 = !a & !b & !c & !d;
-- Node name is ':377'
-- Equation name is '_LC2_E17', type is buried
_LC2_E17 = LCELL( _EQ005);
_EQ005 = b & !c
# !b & c
# d
# !a & b
# !a & c;
-- Node name is ':408'
-- Equation name is '_LC3_E17', type is buried
_LC3_E17 = LCELL( _EQ006);
_EQ006 = _LC6_E17
# _LC1_E17;
-- Node name is ':410'
-- Equation name is '_LC6_E17', type is buried
!_LC6_E17 = _LC6_E17~NOT;
_LC6_E17~NOT = LCELL( _EQ007);
_EQ007 = b & !c & !d
# a & !c & !d;
-- Node name is '~441~1'
-- Equation name is '~441~1', location is LC8_E17, type is buried.
-- synthesized logic cell
_LC8_E17 = LCELL( _EQ008);
_EQ008 = b & d
# c & d
# !a & b
# !a & !c
# !a & d
# !b & !c & !d;
-- Node name is ':441'
-- Equation name is '_LC7_E17', type is buried
_LC7_E17 = LCELL( _EQ009);
_EQ009 = !_LC5_E17 & _LC8_E17
# _LC1_E17;
-- Node name is ':474'
-- Equation name is '_LC2_E16', type is buried
_LC2_E16 = LCELL( _EQ010);
_EQ010 = d
# !a & b
# !a & !c
# b & !c
# a & !b & c;
-- Node name is ':530'
-- Equation name is '_LC1_E16', type is buried
_LC1_E16 = LCELL( _EQ011);
_EQ011 = d
# !c
# !a & !b
# a & b;
-- Node name is ':540'
-- Equation name is '_LC1_E13', type is buried
_LC1_E13 = LCELL( _EQ012);
_EQ012 = !_LC6_E17
# _LC1_E16
# _LC4_E17
# _LC1_E17;
-- Node name is ':573'
-- Equation name is '_LC4_E13', type is buried
_LC4_E13 = LCELL( _EQ013);
_EQ013 = _LC1_E17
# !_LC4_E17 & !_LC5_E17;
Project Information d:\bahe\qiduanyima.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,658K
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