📄 zonghejishu.rpt
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Device-Specific Information: e:\bahe1\yima\zonghejishu.rpt
zonghejishu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - E 13 DFFE 5 0 0 1 |dchufa:i1|:3
- 1 - E 21 AND2 0 3 0 1 |jishu16:g1|LPM_ADD_SUB:58|addcore:adder|:59
- 4 - E 21 OR2 0 3 0 1 |jishu16:g1|LPM_ADD_SUB:79|addcore:adder|pcarry2
- 2 - E 21 DFFE 1 4 1 0 |jishu16:g1|temp3 (|jishu16:g1|:8)
- 8 - E 21 DFFE 1 4 1 2 |jishu16:g1|temp2 (|jishu16:g1|:9)
- 5 - E 21 DFFE 1 3 1 3 |jishu16:g1|temp1 (|jishu16:g1|:10)
- 3 - E 21 DFFE 1 1 1 4 |jishu16:g1|temp0 (|jishu16:g1|:11)
- 1 - E 13 DFFE 3 1 0 3 |jkslect:u1|jout (|jkslect:u1|:5)
- 5 - E 13 OR2 4 0 0 1 :58
- 3 - E 13 OR2 s 2 0 0 1 ~72~1
- 2 - E 13 AND2 0 2 0 4 :73
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bahe1\yima\zonghejishu.rpt
zonghejishu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 3/ 96( 3%) 0/ 48( 0%) 8/ 48( 16%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
F: 2/ 96( 2%) 0/ 48( 0%) 1/ 48( 2%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bahe1\yima\zonghejishu.rpt
zonghejishu
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 4 :73
INPUT 2 cp
Device-Specific Information: e:\bahe1\yima\zonghejishu.rpt
zonghejishu
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clear
Device-Specific Information: e:\bahe1\yima\zonghejishu.rpt
zonghejishu
** EQUATIONS **
bego : INPUT;
clear : INPUT;
cp : INPUT;
left : INPUT;
over : INPUT;
right : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC3_E21;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC5_E21;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC8_E21;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC2_E21;
-- Node name is '|dchufa:i1|:3'
-- Equation name is '_LC4_E13', type is buried
_LC4_E13 = DFFE( _EQ001, cp, VCC, VCC, VCC);
_EQ001 = bego & !left & !over & right
# bego & left & !over & !right;
-- Node name is '|jishu16:g1|LPM_ADD_SUB:58|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_E21', type is buried
_LC1_E21 = LCELL( _EQ002);
_EQ002 = _LC3_E21 & _LC5_E21 & _LC8_E21;
-- Node name is '|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_E21', type is buried
_LC4_E21 = LCELL( _EQ003);
_EQ003 = _LC8_E21
# _LC3_E21
# _LC5_E21;
-- Node name is '|jishu16:g1|:11' = '|jishu16:g1|temp0'
-- Equation name is '_LC3_E21', type is buried
_LC3_E21 = DFFE(!_LC3_E21, _LC2_E13, !clear, VCC, VCC);
-- Node name is '|jishu16:g1|:10' = '|jishu16:g1|temp1'
-- Equation name is '_LC5_E21', type is buried
_LC5_E21 = DFFE( _EQ004, _LC2_E13, !clear, VCC, VCC);
_EQ004 = !_LC1_E13 & _LC3_E21 & _LC5_E21
# _LC1_E13 & _LC3_E21 & !_LC5_E21
# _LC1_E13 & !_LC3_E21 & _LC5_E21
# !_LC1_E13 & !_LC3_E21 & !_LC5_E21;
-- Node name is '|jishu16:g1|:9' = '|jishu16:g1|temp2'
-- Equation name is '_LC8_E21', type is buried
_LC8_E21 = DFFE( _EQ005, _LC2_E13, !clear, VCC, VCC);
_EQ005 = _LC1_E13 & !_LC3_E21 & _LC8_E21
# _LC1_E13 & !_LC5_E21 & _LC8_E21
# _LC1_E13 & _LC3_E21 & _LC5_E21 & !_LC8_E21
# !_LC1_E13 & _LC3_E21 & _LC8_E21
# !_LC1_E13 & _LC5_E21 & _LC8_E21
# !_LC1_E13 & !_LC3_E21 & !_LC5_E21 & !_LC8_E21;
-- Node name is '|jishu16:g1|:8' = '|jishu16:g1|temp3'
-- Equation name is '_LC2_E21', type is buried
_LC2_E21 = DFFE( _EQ006, _LC2_E13, !clear, VCC, VCC);
_EQ006 = _LC1_E13 & !_LC1_E21 & _LC2_E21
# _LC1_E13 & _LC1_E21 & !_LC2_E21
# !_LC1_E13 & _LC2_E21 & _LC4_E21
# !_LC1_E13 & !_LC2_E21 & !_LC4_E21;
-- Node name is '|jkslect:u1|:5' = '|jkslect:u1|jout'
-- Equation name is '_LC1_E13', type is buried
_LC1_E13 = DFFE( _EQ007, cp, VCC, VCC, VCC);
_EQ007 = !_LC3_E13 & left & !right
# _LC1_E13 & left
# _LC1_E13 & _LC3_E13
# _LC1_E13 & !right;
-- Node name is ':58'
-- Equation name is '_LC5_E13', type is buried
_LC5_E13 = LCELL( _EQ008);
_EQ008 = bego & !left & !over & right
# bego & left & !over & !right;
-- Node name is '~72~1'
-- Equation name is '~72~1', location is LC3_E13, type is buried.
-- synthesized logic cell
_LC3_E13 = LCELL( _EQ009);
_EQ009 = !bego
# over;
-- Node name is ':73'
-- Equation name is '_LC2_E13', type is buried
_LC2_E13 = LCELL( _EQ010);
_EQ010 = _LC4_E13 & _LC5_E13;
Project Information e:\bahe1\yima\zonghejishu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,169K
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