📄 yima.rpt
字号:
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - E 22 AND2 4 0 1 0 :773
- 2 - E 22 AND2 4 0 1 0 :785
- 1 - E 19 AND2 4 0 1 0 :797
- 7 - E 24 AND2 4 0 1 0 :809
- 6 - E 24 AND2 4 0 1 0 :821
- 5 - E 24 AND2 4 0 1 0 :833
- 3 - E 22 AND2 4 0 1 0 :845
- 1 - E 22 AND2 4 0 1 0 :857
- 2 - E 24 AND2 4 0 1 0 :869
- 4 - E 24 AND2 4 0 1 0 :881
- 6 - E 22 AND2 4 0 1 0 :893
- 5 - E 19 AND2 4 0 1 0 :905
- 3 - E 24 AND2 4 0 1 0 :917
- 1 - E 24 AND2 4 0 1 0 :929
- 8 - E 24 AND2 4 0 1 0 :1318
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\20050820113\bahe1\yima.rpt
yima
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 1/16( 6%) 0/16( 0%) 3/16( 18%)
E: 2/ 96( 2%) 0/ 48( 0%) 6/ 48( 12%) 2/16( 12%) 0/16( 0%) 4/16( 25%)
F: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 0/16( 0%) 4/16( 25%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
24: 5/24( 20%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\20050820113\bahe1\yima.rpt
yima
** EQUATIONS **
a : INPUT;
b : INPUT;
c : INPUT;
d : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is bidir
y0 = TRI(_LC5_E24, VCC);
-- Node name is 'y1'
-- Equation name is 'y1', type is bidir
y1 = TRI(_LC6_E24, VCC);
-- Node name is 'y2'
-- Equation name is 'y2', type is bidir
y2 = TRI(_LC7_E24, VCC);
-- Node name is 'y3'
-- Equation name is 'y3', type is bidir
y3 = TRI(_LC1_E19, VCC);
-- Node name is 'y4'
-- Equation name is 'y4', type is bidir
y4 = TRI(_LC2_E22, VCC);
-- Node name is 'y5'
-- Equation name is 'y5', type is bidir
y5 = TRI(_LC5_E22, VCC);
-- Node name is 'y6'
-- Equation name is 'y6', type is bidir
y6 = TRI(_LC8_E24, VCC);
-- Node name is 'y7'
-- Equation name is 'y7', type is bidir
y7 = TRI(_LC1_E24, VCC);
-- Node name is 'y8'
-- Equation name is 'y8', type is bidir
y8 = TRI(_LC3_E24, VCC);
-- Node name is 'y9'
-- Equation name is 'y9', type is bidir
y9 = TRI(_LC5_E19, VCC);
-- Node name is 'y10'
-- Equation name is 'y10', type is bidir
y10 = TRI(_LC6_E22, VCC);
-- Node name is 'y11'
-- Equation name is 'y11', type is bidir
y11 = TRI(_LC4_E24, VCC);
-- Node name is 'y12'
-- Equation name is 'y12', type is bidir
y12 = TRI(_LC2_E24, VCC);
-- Node name is 'y13'
-- Equation name is 'y13', type is bidir
y13 = TRI(_LC1_E22, VCC);
-- Node name is 'y14'
-- Equation name is 'y14', type is bidir
y14 = TRI(_LC3_E22, VCC);
-- Node name is ':773'
-- Equation name is '_LC5_E22', type is buried
_LC5_E22 = LCELL( _EQ001);
_EQ001 = !a & b & c & d;
-- Node name is ':785'
-- Equation name is '_LC2_E22', type is buried
_LC2_E22 = LCELL( _EQ002);
_EQ002 = a & !b & c & d;
-- Node name is ':797'
-- Equation name is '_LC1_E19', type is buried
_LC1_E19 = LCELL( _EQ003);
_EQ003 = !a & !b & c & d;
-- Node name is ':809'
-- Equation name is '_LC7_E24', type is buried
_LC7_E24 = LCELL( _EQ004);
_EQ004 = a & b & !c & d;
-- Node name is ':821'
-- Equation name is '_LC6_E24', type is buried
_LC6_E24 = LCELL( _EQ005);
_EQ005 = !a & b & !c & d;
-- Node name is ':833'
-- Equation name is '_LC5_E24', type is buried
_LC5_E24 = LCELL( _EQ006);
_EQ006 = a & !b & !c & d;
-- Node name is ':845'
-- Equation name is '_LC3_E22', type is buried
_LC3_E22 = LCELL( _EQ007);
_EQ007 = a & b & c & !d;
-- Node name is ':857'
-- Equation name is '_LC1_E22', type is buried
_LC1_E22 = LCELL( _EQ008);
_EQ008 = !a & b & c & !d;
-- Node name is ':869'
-- Equation name is '_LC2_E24', type is buried
_LC2_E24 = LCELL( _EQ009);
_EQ009 = a & !b & c & !d;
-- Node name is ':881'
-- Equation name is '_LC4_E24', type is buried
_LC4_E24 = LCELL( _EQ010);
_EQ010 = !a & !b & c & !d;
-- Node name is ':893'
-- Equation name is '_LC6_E22', type is buried
_LC6_E22 = LCELL( _EQ011);
_EQ011 = a & b & !c & !d;
-- Node name is ':905'
-- Equation name is '_LC5_E19', type is buried
_LC5_E19 = LCELL( _EQ012);
_EQ012 = !a & b & !c & !d;
-- Node name is ':917'
-- Equation name is '_LC3_E24', type is buried
_LC3_E24 = LCELL( _EQ013);
_EQ013 = a & !b & !c & !d;
-- Node name is ':929'
-- Equation name is '_LC1_E24', type is buried
_LC1_E24 = LCELL( _EQ014);
_EQ014 = !a & !b & !c & !d;
-- Node name is ':1318'
-- Equation name is '_LC8_E24', type is buried
_LC8_E24 = LCELL( _EQ015);
_EQ015 = a & b & c & d;
Project Information d:\20050820113\bahe1\yima.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,928K
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