📄 baheyouxi.rpt
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_EQ032 = bego & _LC021 & !_LC022 & _LC031 & _X003 & _X004
# bego & !_LC021 & _LC022 & !_LC031 & _X003 & _X004;
_X003 = EXP(!_LC018 & !_LC019 & _LC020 & _LC023);
_X004 = EXP( _LC018 & _LC019 & !_LC020 & _LC023);
-- Node name is '|HEXIN:26|zonghejishu:u1|~60~1'
-- Equation name is '_LC047', type is buried
-- synthesized logic cell
_LC047 = LCELL( _EQ033 $ GND);
_EQ033 = bego & !_LC021 & _LC022 & _X003 & _X004
# bego & _LC021 & !_LC022 & _X003 & _X004;
_X003 = EXP(!_LC018 & !_LC019 & _LC020 & _LC023);
_X004 = EXP( _LC018 & _LC019 & !_LC020 & _LC023);
-- Node name is '|JICUNQI:27|dchufa:u1|:3'
-- Equation name is '_LC001', type is buried
_LC001 = DFFE( left $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|dchufa:u2|:3'
-- Equation name is '_LC039', type is buried
_LC039 = DFFE( _LC001 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|dchufa:u3|:3'
-- Equation name is '_LC028', type is buried
_LC028 = DFFE( _LC039 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|dchufa:u4|:3'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _LC028 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|~112~1'
-- Equation name is '_LC022', type is buried
-- synthesized logic cell
_LC022 = LCELL( _EQ034 $ GND);
_EQ034 = bego & _LC001 & _LC028 & _LC029 & _LC039
# bego & _LC022 & _LC039
# bego & _LC022 & _LC028
# bego & _LC022 & _LC029
# bego & _LC001 & _LC022;
-- Node name is '|JICUNQI:28|dchufa:u1|:3'
-- Equation name is '_LC006', type is buried
_LC006 = DFFE( right $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|dchufa:u2|:3'
-- Equation name is '_LC032', type is buried
_LC032 = DFFE( _LC006 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|dchufa:u3|:3'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( _LC032 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|dchufa:u4|:3'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _LC027 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|~112~1'
-- Equation name is '_LC021', type is buried
-- synthesized logic cell
_LC021 = LCELL( _EQ035 $ GND);
_EQ035 = bego & _LC006 & _LC026 & _LC027 & _LC032
# bego & _LC021 & _LC032
# bego & _LC021 & _LC027
# bego & _LC021 & _LC026
# bego & _LC006 & _LC021;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~328~1'
-- Equation name is '_LC063', type is buried
-- synthesized logic cell
_LC063 = LCELL( _EQ036 $ GND);
_EQ036 = _LC042 & you
# _LC054 & !you;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~337~1'
-- Equation name is '_LC058', type is buried
-- synthesized logic cell
_LC058 = LCELL( _EQ037 $ GND);
_EQ037 = _LC038 & you
# _LC050 & !you;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~346~1'
-- Equation name is '_LC059', type is buried
-- synthesized logic cell
_LC059 = LCELL( _EQ038 $ GND);
_EQ038 = _LC043 & you
# _LC055 & !you;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~355~1'
-- Equation name is '_LC060', type is buried
-- synthesized logic cell
_LC060 = LCELL( _EQ039 $ GND);
_EQ039 = _LC034 & you
# _LC045 & !you;
-- Node name is '|XIANSHI:20|jishu10:k1|:11' = '|XIANSHI:20|jishu10:k1|count0'
-- Equation name is '_LC045', type is buried
_LC045 = TFFE( bego, _EQ040, !clearxianshi, VCC, VCC);
_EQ040 = _LC018 & _LC019 & !_LC020 & _LC023;
-- Node name is '|XIANSHI:20|jishu10:k1|:10' = '|XIANSHI:20|jishu10:k1|count1'
-- Equation name is '_LC055', type is buried
_LC055 = TFFE( _EQ041, _EQ042, !clearxianshi, VCC, VCC);
_EQ041 = bego & _LC045 & _LC050 & !_LC055
# bego & _LC045 & !_LC054 & !_LC055
# bego & _LC045 & _LC055;
_EQ042 = _LC018 & _LC019 & !_LC020 & _LC023;
-- Node name is '|XIANSHI:20|jishu10:k1|:9' = '|XIANSHI:20|jishu10:k1|count2'
-- Equation name is '_LC050', type is buried
_LC050 = TFFE( _EQ043, _EQ044, !clearxianshi, VCC, VCC);
_EQ043 = bego & _LC045 & _LC055;
_EQ044 = _LC018 & _LC019 & !_LC020 & _LC023;
-- Node name is '|XIANSHI:20|jishu10:k1|:8' = '|XIANSHI:20|jishu10:k1|count3'
-- Equation name is '_LC054', type is buried
_LC054 = TFFE( _EQ045, _EQ046, !clearxianshi, VCC, VCC);
_EQ045 = bego & _LC045 & !_LC050 & _LC054 & !_LC055
# bego & _LC045 & _LC050 & _LC055;
_EQ046 = _LC018 & _LC019 & !_LC020 & _LC023;
-- Node name is '|XIANSHI:20|jishu10:k2|:11' = '|XIANSHI:20|jishu10:k2|count0'
-- Equation name is '_LC034', type is buried
_LC034 = TFFE( bego, _EQ047, !clearxianshi, VCC, VCC);
_EQ047 = !_LC018 & !_LC019 & _LC020 & _LC023;
-- Node name is '|XIANSHI:20|jishu10:k2|:10' = '|XIANSHI:20|jishu10:k2|count1'
-- Equation name is '_LC043', type is buried
_LC043 = TFFE( _EQ048, _EQ049, !clearxianshi, VCC, VCC);
_EQ048 = bego & _LC034 & _LC038 & !_LC043
# bego & _LC034 & !_LC042 & !_LC043
# bego & _LC034 & _LC043;
_EQ049 = !_LC018 & !_LC019 & _LC020 & _LC023;
-- Node name is '|XIANSHI:20|jishu10:k2|:9' = '|XIANSHI:20|jishu10:k2|count2'
-- Equation name is '_LC038', type is buried
_LC038 = TFFE( _EQ050, _EQ051, !clearxianshi, VCC, VCC);
_EQ050 = bego & _LC034 & _LC043;
_EQ051 = !_LC018 & !_LC019 & _LC020 & _LC023;
-- Node name is '|XIANSHI:20|jishu10:k2|:8' = '|XIANSHI:20|jishu10:k2|count3'
-- Equation name is '_LC042', type is buried
_LC042 = TFFE( _EQ052, _EQ053, !clearxianshi, VCC, VCC);
_EQ052 = bego & _LC034 & !_LC038 & _LC042 & !_LC043
# bego & _LC034 & _LC038 & _LC043;
_EQ053 = !_LC018 & !_LC019 & _LC020 & _LC023;
-- Node name is '|XIANSHI:20|qiduanyima:g1|~360~1'
-- Equation name is '_LC061', type is buried
-- synthesized logic cell
_LC061 = LCELL( _EQ054 $ GND);
_EQ054 = !_LC038 & !_LC042 & !_LC043 & _LC060 & you
# !_LC050 & !_LC054 & !_LC055 & _LC060 & !you;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X003 occurs in LABs B, C
-- _X004 occurs in LABs B, C
Project Information d:\20050820113\bahe1\baheyouxi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,481K
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