📄 baheyouxi.rpt
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Device-Specific Information: d:\20050820113\bahe1\baheyouxi.rpt
baheyouxi
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 16 A OUTPUT t 0 0 0 0 0 0 0 di
25 35 C OUTPUT t 0 0 0 0 4 0 0 q0
26 36 C OUTPUT t 0 0 0 0 4 0 0 q1
28 40 C OUTPUT t 0 0 0 0 4 0 0 q2
29 41 C OUTPUT t 0 0 0 0 4 0 0 q3
24 33 C OUTPUT t 0 0 0 0 4 0 0 q4
27 37 C OUTPUT t 0 0 0 0 4 0 0 q5
31 46 C OUTPUT t 0 0 0 0 4 0 0 q6
32 48 C OUTPUT t 0 0 0 0 4 0 0 q7
21 17 B OUTPUT t 0 0 0 0 4 0 0 q8
14 30 B OUTPUT t 0 0 0 0 4 0 0 q9
16 25 B OUTPUT t 0 0 0 0 4 0 0 q10
17 24 B OUTPUT t 0 0 0 0 4 0 0 q11
8 5 A OUTPUT t 0 0 0 0 4 0 0 q12
9 4 A OUTPUT t 0 0 0 0 4 0 0 q13
11 3 A OUTPUT t 0 0 0 0 4 0 0 q14
5 14 A FF t 0 0 0 1 0 5 5 you (|XIANSHI:20|jishu2:d1|:4)
36 52 D OUTPUT t 1 1 0 0 11 0 0 y0
37 53 D OUTPUT t 1 1 0 0 5 0 0 y1
40 62 D OUTPUT t 1 1 0 0 5 0 0 y2
39 57 D OUTPUT t 1 1 0 0 11 0 0 y3
38 56 D OUTPUT t 2 1 1 0 11 0 0 y4
34 51 D OUTPUT t 1 1 0 0 11 0 0 y5
33 49 D OUTPUT t 2 1 0 0 5 0 0 y6
41 64 D FF t ! 0 0 0 1 1 0 0 zuo (|XIANSHI:20|jishu2:d1|~4~1)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\20050820113\bahe1\baheyouxi.rpt
baheyouxi
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 44 C DFFE + t 2 2 0 1 6 0 4 |HEXIN:26|zonghejishu:u1|dchufa:i1|:3
- 9 A SOFT t 0 0 0 0 2 0 1 |HEXIN:26|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2
(19) 20 B TFFE t 0 0 0 1 7 15 14 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:8)
(20) 19 B TFFE t 4 4 0 2 8 15 16 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:9)
- 18 B TFFE t 4 4 0 2 8 15 16 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:10)
- 23 B TFFE t 4 4 0 2 7 15 15 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:11)
- 31 B TFFE + t 2 2 0 1 7 0 4 |HEXIN:26|zonghejishu:u1|jkslect:u1|jout (|HEXIN:26|zonghejishu:u1|jkslect:u1|:5)
- 47 C SOFT s t 2 2 0 1 6 0 1 |HEXIN:26|zonghejishu:u1|~60~1
(12) 1 A DFFE + t 0 0 0 1 0 0 2 |JICUNQI:27|dchufa:u1|:3
- 39 C DFFE + t 0 0 0 0 1 0 2 |JICUNQI:27|dchufa:u2|:3
- 28 B DFFE + t 0 0 0 0 1 0 2 |JICUNQI:27|dchufa:u3|:3
- 29 B DFFE + t 0 0 0 0 1 0 1 |JICUNQI:27|dchufa:u4|:3
- 22 B LCELL s t 1 0 1 1 5 0 7 |JICUNQI:27|~112~1
- 6 A DFFE + t 0 0 0 1 0 0 2 |JICUNQI:28|dchufa:u1|:3
(13) 32 B DFFE + t 0 0 0 0 1 0 2 |JICUNQI:28|dchufa:u2|:3
- 27 B DFFE + t 0 0 0 0 1 0 2 |JICUNQI:28|dchufa:u3|:3
- 26 B DFFE + t 0 0 0 0 1 0 1 |JICUNQI:28|dchufa:u4|:3
(18) 21 B LCELL s t 1 0 1 1 5 0 7 |JICUNQI:28|~112~1
- 63 D LCELL s t 0 0 0 0 3 7 0 |XIANSHI:20|duolufuyong:w1|~328~1
- 58 D LCELL s t 0 0 0 0 3 7 0 |XIANSHI:20|duolufuyong:w1|~337~1
- 59 D LCELL s t 0 0 0 0 3 7 0 |XIANSHI:20|duolufuyong:w1|~346~1
- 60 D LCELL s t 0 0 0 0 3 7 1 |XIANSHI:20|duolufuyong:w1|~355~1
- 54 D TFFE t 0 0 0 2 8 4 4 |XIANSHI:20|jishu10:k1|count3 (|XIANSHI:20|jishu10:k1|:8)
- 50 D TFFE t 0 0 0 2 6 4 4 |XIANSHI:20|jishu10:k1|count2 (|XIANSHI:20|jishu10:k1|:9)
- 55 D TFFE t 1 0 1 2 8 4 5 |XIANSHI:20|jishu10:k1|count1 (|XIANSHI:20|jishu10:k1|:10)
- 45 C TFFE t 0 0 0 2 4 0 4 |XIANSHI:20|jishu10:k1|count0 (|XIANSHI:20|jishu10:k1|:11)
- 42 C TFFE t 0 0 0 2 8 4 4 |XIANSHI:20|jishu10:k2|count3 (|XIANSHI:20|jishu10:k2|:8)
- 38 C TFFE t 0 0 0 2 6 4 4 |XIANSHI:20|jishu10:k2|count2 (|XIANSHI:20|jishu10:k2|:9)
- 43 C TFFE t 1 0 1 2 8 4 5 |XIANSHI:20|jishu10:k2|count1 (|XIANSHI:20|jishu10:k2|:10)
- 34 C TFFE t 0 0 0 2 4 0 4 |XIANSHI:20|jishu10:k2|count0 (|XIANSHI:20|jishu10:k2|:11)
- 61 D SOFT s t 0 0 0 0 8 3 0 |XIANSHI:20|qiduanyima:g1|~360~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\20050820113\bahe1\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC16 di
| +------------- LC9 |HEXIN:26|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2
| | +----------- LC1 |JICUNQI:27|dchufa:u1|:3
| | | +--------- LC6 |JICUNQI:28|dchufa:u1|:3
| | | | +------- LC5 q12
| | | | | +----- LC4 q13
| | | | | | +--- LC3 q14
| | | | | | | +- LC14 you
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
Pin
20 -> - - - - - - - * | * - - * | <-- clk1
43 -> - - - - - - - - | - - - - | <-- cp
6 -> - - * - - - - - | * - - - | <-- left
7 -> - - - * - - - - | * - - - | <-- right
LC20 -> - - - - * * * - | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
LC19 -> - * - - * * * - | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
LC18 -> - * - - * * * - | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
LC23 -> - - - - * * * - | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\20050820113\bahe1\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC20 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
| +----------------------------- LC19 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
| | +--------------------------- LC18 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
| | | +------------------------- LC23 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
| | | | +----------------------- LC31 |HEXIN:26|zonghejishu:u1|jkslect:u1|jout
| | | | | +--------------------- LC28 |JICUNQI:27|dchufa:u3|:3
| | | | | | +------------------- LC29 |JICUNQI:27|dchufa:u4|:3
| | | | | | | +----------------- LC22 |JICUNQI:27|~112~1
| | | | | | | | +--------------- LC32 |JICUNQI:28|dchufa:u2|:3
| | | | | | | | | +------------- LC27 |JICUNQI:28|dchufa:u3|:3
| | | | | | | | | | +----------- LC26 |JICUNQI:28|dchufa:u4|:3
| | | | | | | | | | | +--------- LC21 |JICUNQI:28|~112~1
| | | | | | | | | | | | +------- LC17 q8
| | | | | | | | | | | | | +----- LC30 q9
| | | | | | | | | | | | | | +--- LC25 q10
| | | | | | | | | | | | | | | +- LC24 q11
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC20 -> * * * * * - - - - - - - * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
LC19 -> * * * * * - - - - - - - * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
LC18 -> * * * * * - - - - - - - * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
LC23 -> * * * * * - - - - - - - * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
LC31 -> * * * - * - - - - - - - - - - - | - * - - | <-- |HEXIN:26|zonghejishu:u1|jkslect:u1|jout
LC28 -> - - - - - - * * - - - - - - - - | - * - - | <-- |JICUNQI:27|dchufa:u3|:3
LC29 -> - - - - - - - * - - - - - - - - | - * - - | <-- |JICUNQI:27|dchufa:u4|:3
LC22 -> - * * * * - - * - - - - - - - - | - * * - | <-- |JICUNQI:27|~112~1
LC32 -> - - - - - - - - - * - * - - - - | - * - - | <-- |JICUNQI:28|dchufa:u2|:3
LC27 -> - - - - - - - - - - * * - - - - | - * - - | <-- |JICUNQI:28|dchufa:u3|:3
LC26 -> - - - - - - - - - - - * - - - - | - * - - | <-- |JICUNQI:28|dchufa:u4|:3
LC21 -> - * * * * - - - - - - * - - - - | - * * - | <-- |JICUNQI:28|~112~1
Pin
12 -> - * * * * - - * - - - * - - - - | - * * * | <-- bego
19 -> * * * * - - - - - - - - - - - - | - * - - | <-- clearhexin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- cp
LC44 -> * * * * - - - - - - - - - - - - | - * - - | <-- |HEXIN:26|zonghejishu:u1|dchufa:i1|:3
LC9 -> * - - - - - - - - - - - - - - - | - * - - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2
LC47 -> * - - - - - - - - - - - - - - - | - * - - | <-- |HEXIN:26|zonghejishu:u1|~60~1
LC1 -> - - - - - - - * - - - - - - - - | - * * - | <-- |JICUNQI:27|dchufa:u1|:3
LC39 -> - - - - - * - * - - - - - - - - | - * - - | <-- |JICUNQI:27|dchufa:u2|:3
LC6 -> - - - - - - - - * - - * - - - - | - * - - | <-- |JICUNQI:28|dchufa:u1|:3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\20050820113\bahe1\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC44 |HEXIN:26|zonghejishu:u1|dchufa:i1|:3
| +----------------------------- LC47 |HEXIN:26|zonghejishu:u1|~60~1
| | +--------------------------- LC39 |JICUNQI:27|dchufa:u2|:3
| | | +------------------------- LC35 q0
| | | | +----------------------- LC36 q1
| | | | | +--------------------- LC40 q2
| | | | | | +------------------- LC41 q3
| | | | | | | +----------------- LC33 q4
| | | | | | | | +--------------- LC37 q5
| | | | | | | | | +------------- LC46 q6
| | | | | | | | | | +----------- LC48 q7
| | | | | | | | | | | +--------- LC45 |XIANSHI:20|jishu10:k1|count0
| | | | | | | | | | | | +------- LC42 |XIANSHI:20|jishu10:k2|count3
| | | | | | | | | | | | | +----- LC38 |XIANSHI:20|jishu10:k2|count2
| | | | | | | | | | | | | | +--- LC43 |XIANSHI:20|jishu10:k2|count1
| | | | | | | | | | | | | | | +- LC34 |XIANSHI:20|jishu10:k2|count0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC42 -> - - - - - - - - - - - - * - * - | - - * * | <-- |XIANSHI:20|jishu10:k2|count3
LC38 -> - - - - - - - - - - - - * * * - | - - * * | <-- |XIANSHI:20|jishu10:k2|count2
LC43 -> - - - - - - - - - - - - * * * - | - - * * | <-- |XIANSHI:20|jishu10:k2|count1
LC34 -> - - - - - - - - - - - - * * * * | - - * * | <-- |XIANSHI:20|jishu10:k2|count0
Pin
12 -> * * - - - - - - - - - * * * * * | - * * * | <-- bego
18 -> - - - - - - - - - - - * * * * * | - - * * | <-- clearxianshi
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- cp
LC20 -> * * - * * * * * * * * * * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
LC19 -> * * - * * * * * * * * * * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
LC18 -> * * - * * * * * * * * * * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
LC23 -> * * - * * * * * * * * * * * * * | * * * * | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
LC1 -> - - * - - - - - - - - - - - - - | - * * - | <-- |JICUNQI:27|dchufa:u1|:3
LC22 -> * * - - - - - - - - - - - - - - | - * * - | <-- |JICUNQI:27|~112~1
LC21 -> * * - - - - - - - - - - - - - - | - * * - | <-- |JICUNQI:28|~112~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\20050820113\bahe1\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC63 |XIANSHI:20|duolufuyong:w1|~328~1
| +----------------------------- LC58 |XIANSHI:20|duolufuyong:w1|~337~1
| | +--------------------------- LC59 |XIANSHI:20|duolufuyong:w1|~346~1
| | | +------------------------- LC60 |XIANSHI:20|duolufuyong:w1|~355~1
| | | | +----------------------- LC54 |XIANSHI:20|jishu10:k1|count3
| | | | | +--------------------- LC50 |XIANSHI:20|jishu10:k1|count2
| | | | | | +------------------- LC55 |XIANSHI:20|jishu10:k1|count1
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