📄 jishu16.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\result of exp\luogical experiment\20050820113\bahe1\jishu16.rpt
jishu16
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 16 AND2 0 3 0 1 |LPM_ADD_SUB:58|addcore:adder|:59
- 5 - A 16 OR2 0 3 0 1 |LPM_ADD_SUB:79|addcore:adder|pcarry2
- 4 - A 16 DFFE + 1 2 1 0 temp3 (:8)
- 1 - A 16 DFFE + 1 2 1 2 temp2 (:9)
- 7 - A 16 DFFE + 1 1 1 3 temp1 (:10)
- 2 - A 16 DFFE + 0 0 1 4 temp0 (:11)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\result of exp\luogical experiment\20050820113\bahe1\jishu16.rpt
jishu16
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\result of exp\luogical experiment\20050820113\bahe1\jishu16.rpt
jishu16
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information:e:\result of exp\luogical experiment\20050820113\bahe1\jishu16.rpt
jishu16
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information:e:\result of exp\luogical experiment\20050820113\bahe1\jishu16.rpt
jishu16
** EQUATIONS **
clk : INPUT;
clr : INPUT;
input : INPUT;
-- Node name is 'qa'
-- Equation name is 'qa', type is output
qa = temp0;
-- Node name is 'qb'
-- Equation name is 'qb', type is output
qb = temp1;
-- Node name is 'qc'
-- Equation name is 'qc', type is output
qc = temp2;
-- Node name is 'qd'
-- Equation name is 'qd', type is output
qd = temp3;
-- Node name is ':11' = 'temp0'
-- Equation name is 'temp0', location is LC2_A16, type is buried.
temp0 = DFFE(!temp0, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':10' = 'temp1'
-- Equation name is 'temp1', location is LC7_A16, type is buried.
temp1 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = !input & temp0 & temp1
# input & temp0 & !temp1
# input & !temp0 & temp1
# !input & !temp0 & !temp1;
-- Node name is ':9' = 'temp2'
-- Equation name is 'temp2', location is LC1_A16, type is buried.
temp2 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = input & !temp0 & temp2
# input & !temp1 & temp2
# input & temp0 & temp1 & !temp2
# !input & temp0 & temp2
# !input & temp1 & temp2
# !input & !temp0 & !temp1 & !temp2;
-- Node name is ':8' = 'temp3'
-- Equation name is 'temp3', location is LC4_A16, type is buried.
temp3 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = input & !_LC3_A16 & temp3
# input & _LC3_A16 & !temp3
# !input & _LC5_A16 & temp3
# !input & !_LC5_A16 & !temp3;
-- Node name is '|LPM_ADD_SUB:58|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = LCELL( _EQ004);
_EQ004 = temp0 & temp1 & temp2;
-- Node name is '|LPM_ADD_SUB:79|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ005);
_EQ005 = temp2
# temp0
# temp1;
Project Informatione:\result of exp\luogical experiment\20050820113\bahe1\jishu16.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,857K
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