📄 bahe.rpt
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_LC2_F24 = LCELL( _EQ037);
_EQ037 = !_LC1_F13 & !_LC1_F21 & _LC1_F24;
-- Node name is '|hexin:p1|yima:g1|:1510'
-- Equation name is '_LC7_F22', type is buried
_LC7_F22 = LCELL( _EQ038);
_EQ038 = !_LC4_F22 & _LC7_F21 & _LC8_F22
# _LC2_F23 & !_LC4_F22 & _LC8_F22;
-- Node name is '|hexin:p1|yima:g1|:1531'
-- Equation name is '_LC3_F22', type is buried
_LC3_F22 = LCELL( _EQ039);
_EQ039 = _LC2_F23 & !_LC7_F21;
-- Node name is '|hexin:p1|yima:g1|~1558~1'
-- Equation name is '_LC8_F22', type is buried
-- synthesized logic cell
_LC8_F22 = LCELL( _EQ040);
_EQ040 = _LC2_F24 & !_LC8_F21;
-- Node name is '|hexin:p1|yima:g1|:1558'
-- Equation name is '_LC6_F22', type is buried
_LC6_F22 = LCELL( _EQ041);
_EQ041 = _LC2_F23 & !_LC7_F21 & _LC8_F22
# _LC4_F22 & _LC8_F22;
-- Node name is '|hexin:p1|yima:g1|~1606~1'
-- Equation name is '_LC4_F17', type is buried
-- synthesized logic cell
_LC4_F17 = LCELL( _EQ042);
_EQ042 = !_LC4_F21 & !_LC6_F21;
-- Node name is '|hexin:p1|yima:g1|:1606'
-- Equation name is '_LC5_F22', type is buried
_LC5_F22 = LCELL( _EQ043);
_EQ043 = _LC2_F24 & _LC8_F21
# _LC2_F24 & _LC3_F22 & !_LC4_F22;
-- Node name is '|hexin:p1|zonghejishu:u1|dchufa:i1|:3'
-- Equation name is '_LC8_E14', type is buried
_LC8_E14 = DFFE( _EQ044, cp, VCC, VCC, VCC);
_EQ044 = _LC1_E24 & _LC6_E23 & !_LC7_E14
# _LC1_E24 & !_LC6_E23 & _LC7_E14;
-- Node name is '|hexin:p1|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:58|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_F13', type is buried
!_LC2_F13 = _LC2_F13~NOT;
_LC2_F13~NOT = LCELL( _EQ045);
_EQ045 = !_LC6_F13
# !_LC5_F13
# !_LC4_F13;
-- Node name is '|hexin:p1|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_F13', type is buried
_LC8_F13 = LCELL( _EQ046);
_EQ046 = _LC5_F13
# _LC4_F13
# _LC6_F13;
-- Node name is '|hexin:p1|zonghejishu:u1|jishu16:g1|:11' = '|hexin:p1|zonghejishu:u1|jishu16:g1|temp0'
-- Equation name is '_LC5_F13', type is buried
_LC5_F13 = DFFE(!_LC5_F13, _LC1_E14, !clear, VCC, VCC);
-- Node name is '|hexin:p1|zonghejishu:u1|jishu16:g1|:10' = '|hexin:p1|zonghejishu:u1|jishu16:g1|temp1'
-- Equation name is '_LC4_F13', type is buried
_LC4_F13 = DFFE( _EQ047, _LC1_E14, !clear, VCC, VCC);
_EQ047 = !_LC4_E14 & _LC4_F13 & _LC5_F13
# _LC4_E14 & !_LC4_F13 & _LC5_F13
# _LC4_E14 & _LC4_F13 & !_LC5_F13
# !_LC4_E14 & !_LC4_F13 & !_LC5_F13;
-- Node name is '|hexin:p1|zonghejishu:u1|jishu16:g1|:9' = '|hexin:p1|zonghejishu:u1|jishu16:g1|temp2'
-- Equation name is '_LC6_F13', type is buried
_LC6_F13 = DFFE( _EQ048, _LC1_E14, !clear, VCC, VCC);
_EQ048 = _LC4_E14 & !_LC5_F13 & _LC6_F13
# _LC4_E14 & !_LC4_F13 & _LC6_F13
# _LC4_E14 & _LC4_F13 & _LC5_F13 & !_LC6_F13
# !_LC4_E14 & _LC5_F13 & _LC6_F13
# !_LC4_E14 & _LC4_F13 & _LC6_F13
# !_LC4_E14 & !_LC4_F13 & !_LC5_F13 & !_LC6_F13;
-- Node name is '|hexin:p1|zonghejishu:u1|jishu16:g1|:8' = '|hexin:p1|zonghejishu:u1|jishu16:g1|temp3'
-- Equation name is '_LC7_F13', type is buried
_LC7_F13 = DFFE( _EQ049, _LC1_E14, !clear, VCC, VCC);
_EQ049 = !_LC2_F13 & _LC4_E14 & _LC7_F13
# _LC2_F13 & _LC4_E14 & !_LC7_F13
# !_LC4_E14 & _LC7_F13 & _LC8_F13
# !_LC4_E14 & !_LC7_F13 & !_LC8_F13;
-- Node name is '|hexin:p1|zonghejishu:u1|jkslect:u1|:5' = '|hexin:p1|zonghejishu:u1|jkslect:u1|jout'
-- Equation name is '_LC4_E14', type is buried
_LC4_E14 = DFFE( _EQ050, cp, VCC, VCC, VCC);
_EQ050 = !_LC1_E24 & _LC4_E14
# _LC4_E14 & !_LC6_E23
# _LC4_E14 & _LC7_E14
# _LC1_E24 & !_LC6_E23 & _LC7_E14;
-- Node name is '|hexin:p1|zonghejishu:u1|~67~1'
-- Equation name is '_LC1_E24', type is buried
-- synthesized logic cell
_LC1_E24 = LCELL( _EQ051);
_EQ051 = bego & !q0 & !q14;
-- Node name is '|hexin:p1|zonghejishu:u1|:73'
-- Equation name is '_LC1_E14', type is buried
_LC1_E14 = LCELL( _EQ052);
_EQ052 = _LC1_E24 & _LC6_E23 & !_LC7_E14 & _LC8_E14
# _LC1_E24 & !_LC6_E23 & _LC7_E14 & _LC8_E14;
-- Node name is '|jicunqi:g1|dchufa:u1|:3'
-- Equation name is '_LC1_E17', type is buried
_LC1_E17 = DFFE( left, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g1|dchufa:u2|:3'
-- Equation name is '_LC2_E23', type is buried
_LC2_E23 = DFFE( _LC1_E17, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g1|dchufa:u3|:3'
-- Equation name is '_LC2_E14', type is buried
_LC2_E14 = DFFE( _LC2_E23, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g1|dchufa:u4|:3'
-- Equation name is '_LC3_E14', type is buried
_LC3_E14 = DFFE( _LC2_E14, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g1|:60'
-- Equation name is '_LC6_E14', type is buried
_LC6_E14 = LCELL( _EQ053);
_EQ053 = _LC1_E17 & _LC2_E14 & _LC2_E23 & _LC3_E14;
-- Node name is '|jicunqi:g1|:69'
-- Equation name is '_LC5_E14', type is buried
!_LC5_E14 = _LC5_E14~NOT;
_LC5_E14~NOT = LCELL( _EQ054);
_EQ054 = _LC3_E14
# _LC1_E17
# _LC2_E23
# _LC2_E14;
-- Node name is '|jicunqi:g1|:112'
-- Equation name is '_LC7_E14', type is buried
_LC7_E14 = LCELL( _EQ055);
_EQ055 = bego & !_LC5_E14 & _LC7_E14
# bego & _LC6_E14;
-- Node name is '|jicunqi:g2|dchufa:u1|:3'
-- Equation name is '_LC1_E23', type is buried
_LC1_E23 = DFFE( right, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g2|dchufa:u2|:3'
-- Equation name is '_LC3_E23', type is buried
_LC3_E23 = DFFE( _LC1_E23, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g2|dchufa:u3|:3'
-- Equation name is '_LC4_E23', type is buried
_LC4_E23 = DFFE( _LC3_E23, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g2|dchufa:u4|:3'
-- Equation name is '_LC5_E23', type is buried
_LC5_E23 = DFFE( _LC4_E23, cp, VCC, VCC, VCC);
-- Node name is '|jicunqi:g2|:60'
-- Equation name is '_LC8_E23', type is buried
_LC8_E23 = LCELL( _EQ056);
_EQ056 = _LC1_E23 & _LC3_E23 & _LC4_E23 & _LC5_E23;
-- Node name is '|jicunqi:g2|:69'
-- Equation name is '_LC7_E23', type is buried
!_LC7_E23 = _LC7_E23~NOT;
_LC7_E23~NOT = LCELL( _EQ057);
_EQ057 = _LC5_E23
# _LC1_E23
# _LC3_E23
# _LC4_E23;
-- Node name is '|jicunqi:g2|:112'
-- Equation name is '_LC6_E23', type is buried
_LC6_E23 = LCELL( _EQ058);
_EQ058 = bego & _LC6_E23 & !_LC7_E23
# bego & _LC8_E23;
Project Information e:\bahe1\yima\bahe.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,766K
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