📄 bahe.rpt
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Device-Specific Information: e:\bahe1\yima\bahe.rpt
bahe
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - E -- INPUT 0 0 0 3 bego
87 - - E -- INPUT 0 0 0 4 clear
122 - - - 13 INPUT 0 0 0 10 cp
73 - - - 01 INPUT 0 0 0 1 left
21 - - D -- BIDIR 0 1 0 1 q0
22 - - D -- BIDIR 0 1 0 0 q1
23 - - D -- BIDIR 0 1 0 0 q2
26 - - E -- BIDIR 0 1 0 0 q3
27 - - E -- BIDIR 0 1 0 0 q4
28 - - E -- BIDIR 0 1 0 0 q5
29 - - E -- BIDIR 0 1 0 0 q6
30 - - F -- BIDIR 0 1 0 0 q7
31 - - F -- BIDIR 0 1 0 0 q8
32 - - F -- BIDIR 0 1 0 0 q9
33 - - F -- BIDIR 0 1 0 0 q10
36 - - - 24 BIDIR 0 1 0 0 q11
37 - - - 23 BIDIR 0 1 0 0 q12
38 - - - 22 BIDIR 0 1 0 0 q13
39 - - - 21 BIDIR 0 1 0 1 q14
79 - - F -- INPUT 0 0 0 1 right
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\bahe1\yima\bahe.rpt
bahe
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - D -- TRI 0 1 0 1 q0
22 - - D -- TRI 0 1 0 0 q1
23 - - D -- TRI 0 1 0 0 q2
26 - - E -- TRI 0 1 0 0 q3
27 - - E -- TRI 0 1 0 0 q4
28 - - E -- TRI 0 1 0 0 q5
29 - - E -- TRI 0 1 0 0 q6
30 - - F -- TRI 0 1 0 0 q7
31 - - F -- TRI 0 1 0 0 q8
32 - - F -- TRI 0 1 0 0 q9
33 - - F -- TRI 0 1 0 0 q10
36 - - - 24 TRI 0 1 0 0 q11
37 - - - 23 TRI 0 1 0 0 q12
38 - - - 22 TRI 0 1 0 0 q13
39 - - - 21 TRI 0 1 0 1 q14
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\bahe1\yima\bahe.rpt
bahe
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - F 20 OR2 ! 0 2 0 1 |hexin:p1|yima:g1|:761
- 3 - F 13 OR2 ! 0 4 0 2 |hexin:p1|yima:g1|:773
- 6 - F 23 OR2 ! 0 4 0 5 |hexin:p1|yima:g1|:785
- 7 - F 23 OR2 ! 0 4 0 5 |hexin:p1|yima:g1|:797
- 7 - F 21 OR2 ! 0 4 0 5 |hexin:p1|yima:g1|:809
- 4 - F 22 OR2 ! 0 4 0 5 |hexin:p1|yima:g1|:821
- 8 - F 21 AND2 0 4 0 4 |hexin:p1|yima:g1|:833
- 1 - F 13 OR2 ! 0 2 0 4 |hexin:p1|yima:g1|:845
- 1 - F 22 AND2 0 4 0 3 |hexin:p1|yima:g1|:850
- 1 - F 21 OR2 ! 0 4 0 4 |hexin:p1|yima:g1|:857
- 7 - F 24 OR2 ! 0 4 0 4 |hexin:p1|yima:g1|:869
- 6 - F 24 OR2 ! 0 4 0 4 |hexin:p1|yima:g1|:881
- 2 - F 21 OR2 ! 0 4 0 4 |hexin:p1|yima:g1|:893
- 7 - F 17 OR2 ! 0 4 0 5 |hexin:p1|yima:g1|:905
- 4 - F 21 OR2 ! 0 4 0 3 |hexin:p1|yima:g1|:917
- 6 - F 21 OR2 ! 0 4 0 3 |hexin:p1|yima:g1|:929
- 5 - F 21 OR2 0 4 1 0 |hexin:p1|yima:g1|:934
- 1 - F 17 AND2 s 0 3 0 3 |hexin:p1|yima:g1|~982~1
- 1 - F 24 AND2 s 0 3 0 3 |hexin:p1|yima:g1|~982~2
- 3 - F 21 OR2 0 4 1 0 |hexin:p1|yima:g1|:982
- 8 - F 24 AND2 0 3 0 3 |hexin:p1|yima:g1|:1015
- 5 - F 24 OR2 0 4 1 0 |hexin:p1|yima:g1|:1030
- 4 - F 24 OR2 0 4 1 0 |hexin:p1|yima:g1|:1078
- 3 - F 24 AND2 0 3 0 3 |hexin:p1|yima:g1|:1117
- 6 - F 17 OR2 0 4 1 0 |hexin:p1|yima:g1|:1126
- 8 - F 17 AND2 0 2 0 2 |hexin:p1|yima:g1|:1168
- 5 - F 17 OR2 0 4 1 0 |hexin:p1|yima:g1|:1174
- 3 - F 17 OR2 0 4 1 0 |hexin:p1|yima:g1|:1222
- 2 - F 17 OR2 0 4 1 0 |hexin:p1|yima:g1|:1268
- 8 - F 23 AND2 0 4 1 0 |hexin:p1|yima:g1|:1318
- 5 - F 23 AND2 0 4 1 0 |hexin:p1|yima:g1|:1366
- 4 - F 23 OR2 0 3 0 3 |hexin:p1|yima:g1|:1378
- 3 - F 23 OR2 0 4 1 0 |hexin:p1|yima:g1|:1414
- 2 - F 22 AND2 s 0 4 0 4 |hexin:p1|yima:g1|~1462~1
- 1 - F 23 OR2 0 4 1 0 |hexin:p1|yima:g1|:1462
- 2 - F 23 AND2 0 3 0 4 |hexin:p1|yima:g1|:1480
- 2 - F 24 AND2 s 0 3 0 3 |hexin:p1|yima:g1|~1510~1
- 7 - F 22 OR2 0 4 1 0 |hexin:p1|yima:g1|:1510
- 3 - F 22 AND2 0 2 0 1 |hexin:p1|yima:g1|:1531
- 8 - F 22 AND2 s 0 2 0 2 |hexin:p1|yima:g1|~1558~1
- 6 - F 22 OR2 0 4 1 0 |hexin:p1|yima:g1|:1558
- 4 - F 17 AND2 s 0 2 0 3 |hexin:p1|yima:g1|~1606~1
- 5 - F 22 OR2 0 4 1 0 |hexin:p1|yima:g1|:1606
- 8 - E 14 DFFE 1 3 0 1 |hexin:p1|zonghejishu:u1|dchufa:i1|:3
- 2 - F 13 OR2 ! 0 3 0 4 |hexin:p1|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:58|addcore:adder|:59
- 8 - F 13 OR2 0 3 0 1 |hexin:p1|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|pcarry2
- 7 - F 13 DFFE 1 4 0 16 |hexin:p1|zonghejishu:u1|jishu16:g1|temp3 (|hexin:p1|zonghejishu:u1|jishu16:g1|:8)
- 6 - F 13 DFFE 1 4 0 15 |hexin:p1|zonghejishu:u1|jishu16:g1|temp2 (|hexin:p1|zonghejishu:u1|jishu16:g1|:9)
- 4 - F 13 DFFE 1 3 0 16 |hexin:p1|zonghejishu:u1|jishu16:g1|temp1 (|hexin:p1|zonghejishu:u1|jishu16:g1|:10)
- 5 - F 13 DFFE 1 1 0 17 |hexin:p1|zonghejishu:u1|jishu16:g1|temp0 (|hexin:p1|zonghejishu:u1|jishu16:g1|:11)
- 4 - E 14 DFFE 1 3 0 3 |hexin:p1|zonghejishu:u1|jkslect:u1|jout (|hexin:p1|zonghejishu:u1|jkslect:u1|:5)
- 1 - E 24 AND2 s 1 2 0 3 |hexin:p1|zonghejishu:u1|~67~1
- 1 - E 14 OR2 0 4 0 4 |hexin:p1|zonghejishu:u1|:73
- 1 - E 17 DFFE 2 0 0 3 |jicunqi:g1|dchufa:u1|:3
- 2 - E 23 DFFE 1 1 0 3 |jicunqi:g1|dchufa:u2|:3
- 2 - E 14 DFFE 1 1 0 3 |jicunqi:g1|dchufa:u3|:3
- 3 - E 14 DFFE 1 1 0 2 |jicunqi:g1|dchufa:u4|:3
- 6 - E 14 AND2 0 4 0 1 |jicunqi:g1|:60
- 5 - E 14 OR2 ! 0 4 0 1 |jicunqi:g1|:69
- 7 - E 14 OR2 1 2 0 3 |jicunqi:g1|:112
- 1 - E 23 DFFE 2 0 0 3 |jicunqi:g2|dchufa:u1|:3
- 3 - E 23 DFFE 1 1 0 3 |jicunqi:g2|dchufa:u2|:3
- 4 - E 23 DFFE 1 1 0 3 |jicunqi:g2|dchufa:u3|:3
- 5 - E 23 DFFE 1 1 0 2 |jicunqi:g2|dchufa:u4|:3
- 8 - E 23 AND2 0 4 0 1 |jicunqi:g2|:60
- 7 - E 23 OR2 ! 0 4 0 1 |jicunqi:g2|:69
- 6 - E 23 OR2 1 2 0 3 |jicunqi:g2|:112
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bahe1\yima\bahe.rpt
bahe
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 0/16( 0%) 3/16( 18%)
E: 4/ 96( 4%) 0/ 48( 0%) 12/ 48( 25%) 2/16( 12%) 0/16( 0%) 4/16( 25%)
F: 3/ 96( 3%) 0/ 48( 0%) 26/ 48( 54%) 1/16( 6%) 0/16( 0%) 4/16( 25%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
22: 4/24( 16%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
23: 4/24( 16%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bahe1\yima\bahe.rpt
bahe
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 cp
LCELL 4 |hexin:p1|zonghejishu:u1|:73
Device-Specific Information: e:\bahe1\yima\bahe.rpt
bahe
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clear
Device-Specific Information: e:\bahe1\yima\bahe.rpt
bahe
** EQUATIONS **
bego : INPUT;
clear : INPUT;
cp : INPUT;
left : INPUT;
right : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is bidir
q0 = TRI(_LC5_F22, VCC);
-- Node name is 'q1'
-- Equation name is 'q1', type is bidir
q1 = TRI(_LC6_F22, VCC);
-- Node name is 'q2'
-- Equation name is 'q2', type is bidir
q2 = TRI(_LC7_F22, VCC);
-- Node name is 'q3'
-- Equation name is 'q3', type is bidir
q3 = TRI(_LC1_F23, VCC);
-- Node name is 'q4'
-- Equation name is 'q4', type is bidir
q4 = TRI(_LC3_F23, VCC);
-- Node name is 'q5'
-- Equation name is 'q5', type is bidir
q5 = TRI(_LC5_F23, VCC);
-- Node name is 'q6'
-- Equation name is 'q6', type is bidir
q6 = TRI(_LC8_F23, VCC);
-- Node name is 'q7'
-- Equation name is 'q7', type is bidir
q7 = TRI(_LC2_F17, VCC);
-- Node name is 'q8'
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