📄 hexin.rpt
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_EQ015 = !_LC3_F22 & !_LC4_F22 & _LC4_F24 & !_LC6_F17;
-- Node name is '|yima:g1|:934'
-- Equation name is '_LC6_F21', type is buried
_LC6_F21 = LCELL( _EQ016);
_EQ016 = _LC1_F17 & _LC1_F24 & !_LC4_F13
# _LC1_F24 & _LC7_F21;
-- Node name is '|yima:g1|:982'
-- Equation name is '_LC2_F22', type is buried
_LC2_F22 = LCELL( _EQ017);
_EQ017 = !_LC1_F13 & !_LC2_F13 & !_LC3_F13 & _LC4_F13
# !_LC1_F13 & _LC2_F13 & _LC3_F13 & !_LC4_F13;
-- Node name is '|yima:g1|:1015'
-- Equation name is '_LC2_F21', type is buried
_LC2_F21 = LCELL( _EQ018);
_EQ018 = _LC4_F13 & _LC7_F21
# !_LC1_F17 & _LC1_F22 & _LC7_F21;
-- Node name is '|yima:g1|:1030'
-- Equation name is '_LC8_F24', type is buried
_LC8_F24 = LCELL( _EQ019);
_EQ019 = _LC2_F21 & _LC4_F24 & !_LC6_F17
# _LC3_F22 & _LC4_F24 & !_LC6_F17;
-- Node name is '|yima:g1|:1078'
-- Equation name is '_LC3_F24', type is buried
_LC3_F24 = LCELL( _EQ020);
_EQ020 = _LC2_F21 & !_LC3_F22 & _LC4_F24
# _LC4_F24 & _LC6_F17;
-- Node name is '|yima:g1|:1117'
-- Equation name is '_LC7_F24', type is buried
_LC7_F24 = LCELL( _EQ021);
_EQ021 = _LC2_F21 & !_LC3_F22 & !_LC6_F17;
-- Node name is '|yima:g1|:1126'
-- Equation name is '_LC6_F24', type is buried
_LC6_F24 = LCELL( _EQ022);
_EQ022 = _LC5_F17 & !_LC6_F19 & _LC7_F24
# _LC4_F17 & _LC5_F17 & !_LC6_F19;
-- Node name is '|yima:g1|:1174'
-- Equation name is '_LC5_F24', type is buried
_LC5_F24 = LCELL( _EQ023);
_EQ023 = !_LC4_F17 & _LC5_F17 & _LC7_F24
# _LC5_F17 & _LC6_F19;
-- Node name is '|yima:g1|:1219'
-- Equation name is '_LC2_F24', type is buried
_LC2_F24 = LCELL( _EQ024);
_EQ024 = !_LC4_F17 & !_LC6_F19 & _LC7_F24;
-- Node name is '|yima:g1|:1222'
-- Equation name is '_LC3_F17', type is buried
_LC3_F17 = LCELL( _EQ025);
_EQ025 = _LC2_F24 & _LC4_F13
# _LC2_F24 & _LC7_F17
# _LC4_F13 & _LC8_F17
# _LC7_F17 & _LC8_F17;
-- Node name is '|yima:g1|:1268'
-- Equation name is '_LC2_F17', type is buried
_LC2_F17 = LCELL( _EQ026);
_EQ026 = !_LC4_F13 & !_LC7_F17
# _LC2_F24 & !_LC8_F17;
-- Node name is '|yima:g1|:1318'
-- Equation name is '_LC8_F21', type is buried
_LC8_F21 = LCELL( _EQ027);
_EQ027 = !_LC1_F21 & _LC1_F22 & _LC2_F14
# !_LC1_F21 & _LC2_F14 & !_LC4_F13;
-- Node name is '|yima:g1|:1366'
-- Equation name is '_LC5_F21', type is buried
_LC5_F21 = LCELL( _EQ028);
_EQ028 = !_LC1_F21 & _LC2_F14 & !_LC4_F13
# !_LC1_F17 & !_LC1_F21 & _LC2_F14;
-- Node name is '|yima:g1|:1378'
-- Equation name is '_LC4_F21', type is buried
_LC4_F21 = LCELL( _EQ029);
_EQ029 = !_LC4_F13
# !_LC1_F17 & _LC1_F22;
-- Node name is '|yima:g1|~1414~1'
-- Equation name is '_LC2_F14', type is buried
-- synthesized logic cell
_LC2_F14 = LCELL( _EQ030);
_EQ030 = !_LC1_F19 & !_LC2_F19 & !_LC3_F19 & _LC4_F14;
-- Node name is '|yima:g1|:1414'
-- Equation name is '_LC3_F21', type is buried
_LC3_F21 = LCELL( _EQ031);
_EQ031 = _LC2_F14 & _LC4_F21
# _LC1_F21 & _LC2_F14;
-- Node name is '|yima:g1|:1429'
-- Equation name is '_LC3_F14', type is buried
_LC3_F14 = LCELL( _EQ032);
_EQ032 = !_LC1_F21 & !_LC4_F13
# !_LC1_F17 & !_LC1_F21 & _LC1_F22;
-- Node name is '|yima:g1|:1462'
-- Equation name is '_LC1_F14', type is buried
_LC1_F14 = LCELL( _EQ033);
_EQ033 = !_LC1_F19 & _LC3_F19 & _LC8_F14
# !_LC1_F19 & _LC3_F14 & _LC8_F14;
-- Node name is '|yima:g1|:1480'
-- Equation name is '_LC6_F14', type is buried
_LC6_F14 = LCELL( _EQ034);
_EQ034 = _LC3_F14 & !_LC3_F19;
-- Node name is '|yima:g1|~1510~1'
-- Equation name is '_LC7_F19', type is buried
-- synthesized logic cell
_LC7_F19 = LCELL( _EQ035);
_EQ035 = _LC1_F24 & _LC4_F13
# !_LC1_F17 & _LC1_F24;
-- Node name is '|yima:g1|~1510~2'
-- Equation name is '_LC8_F14', type is buried
-- synthesized logic cell
_LC8_F14 = LCELL( _EQ036);
_EQ036 = !_LC2_F19 & _LC4_F14;
-- Node name is '|yima:g1|:1510'
-- Equation name is '_LC7_F14', type is buried
_LC7_F14 = LCELL( _EQ037);
_EQ037 = _LC1_F19 & !_LC2_F19 & _LC4_F14
# !_LC2_F19 & _LC4_F14 & _LC6_F14;
-- Node name is '|yima:g1|:1531'
-- Equation name is '_LC8_F19', type is buried
_LC8_F19 = LCELL( _EQ038);
_EQ038 = !_LC1_F19 & _LC6_F14;
-- Node name is '|yima:g1|~1558~1'
-- Equation name is '_LC4_F14', type is buried
-- synthesized logic cell
_LC4_F14 = LCELL( _EQ039);
_EQ039 = _LC1_F24 & _LC4_F13 & !_LC4_F19
# !_LC1_F17 & _LC1_F24 & !_LC4_F19;
-- Node name is '|yima:g1|:1558'
-- Equation name is '_LC5_F14', type is buried
_LC5_F14 = LCELL( _EQ040);
_EQ040 = !_LC1_F19 & _LC4_F14 & _LC6_F14
# _LC2_F19 & _LC4_F14;
-- Node name is '|yima:g1|~1606~1'
-- Equation name is '_LC5_F17', type is buried
-- synthesized logic cell
_LC5_F17 = LCELL( _EQ041);
_EQ041 = _LC4_F13 & !_LC8_F17
# _LC7_F17 & !_LC8_F17;
-- Node name is '|yima:g1|:1606'
-- Equation name is '_LC5_F19', type is buried
_LC5_F19 = LCELL( _EQ042);
_EQ042 = _LC4_F19 & _LC7_F19
# !_LC2_F19 & _LC7_F19 & _LC8_F19;
-- Node name is '|zonghejishu:u1|dchufa:i1|:3'
-- Equation name is '_LC6_F13', type is buried
_LC6_F13 = DFFE( _EQ043, cp, VCC, VCC, VCC);
_EQ043 = bego & !left & !over & right
# bego & left & !over & !right;
-- Node name is '|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:58|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_F17', type is buried
_LC1_F17 = LCELL( _EQ044);
_EQ044 = _LC1_F13 & _LC2_F13 & _LC3_F13;
-- Node name is '|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_F17', type is buried
_LC7_F17 = LCELL( _EQ045);
_EQ045 = _LC1_F13
# _LC2_F13
# _LC3_F13;
-- Node name is '|zonghejishu:u1|jishu16:g1|:11' = '|zonghejishu:u1|jishu16:g1|temp0'
-- Equation name is '_LC1_F13', type is buried
_LC1_F13 = DFFE(!_LC1_F13, _LC8_F13, !clear, VCC, VCC);
-- Node name is '|zonghejishu:u1|jishu16:g1|:10' = '|zonghejishu:u1|jishu16:g1|temp1'
-- Equation name is '_LC2_F13', type is buried
_LC2_F13 = DFFE( _EQ046, _LC8_F13, !clear, VCC, VCC);
_EQ046 = _LC1_F13 & _LC2_F13 & !_LC5_F13
# _LC1_F13 & !_LC2_F13 & _LC5_F13
# !_LC1_F13 & _LC2_F13 & _LC5_F13
# !_LC1_F13 & !_LC2_F13 & !_LC5_F13;
-- Node name is '|zonghejishu:u1|jishu16:g1|:9' = '|zonghejishu:u1|jishu16:g1|temp2'
-- Equation name is '_LC3_F13', type is buried
_LC3_F13 = DFFE( _EQ047, _LC8_F13, !clear, VCC, VCC);
_EQ047 = !_LC1_F13 & _LC3_F13 & _LC5_F13
# !_LC2_F13 & _LC3_F13 & _LC5_F13
# _LC1_F13 & _LC2_F13 & !_LC3_F13 & _LC5_F13
# _LC1_F13 & _LC3_F13 & !_LC5_F13
# _LC2_F13 & _LC3_F13 & !_LC5_F13
# !_LC1_F13 & !_LC2_F13 & !_LC3_F13 & !_LC5_F13;
-- Node name is '|zonghejishu:u1|jishu16:g1|:8' = '|zonghejishu:u1|jishu16:g1|temp3'
-- Equation name is '_LC4_F13', type is buried
_LC4_F13 = DFFE( _EQ048, _LC8_F13, !clear, VCC, VCC);
_EQ048 = !_LC1_F17 & _LC4_F13 & _LC5_F13
# _LC1_F17 & !_LC4_F13 & _LC5_F13
# _LC4_F13 & !_LC5_F13 & _LC7_F17
# !_LC4_F13 & !_LC5_F13 & !_LC7_F17;
-- Node name is '|zonghejishu:u1|jkslect:u1|:5' = '|zonghejishu:u1|jkslect:u1|jout'
-- Equation name is '_LC5_F13', type is buried
_LC5_F13 = DFFE( _EQ049, cp, VCC, VCC, VCC);
_EQ049 = !_LC2_F15 & left & !right
# _LC5_F13 & left
# _LC2_F15 & _LC5_F13
# _LC5_F13 & !right;
-- Node name is '|zonghejishu:u1|:58'
-- Equation name is '_LC7_F13', type is buried
_LC7_F13 = LCELL( _EQ050);
_EQ050 = bego & !left & !over & right
# bego & left & !over & !right;
-- Node name is '|zonghejishu:u1|~72~1'
-- Equation name is '_LC2_F15', type is buried
-- synthesized logic cell
_LC2_F15 = LCELL( _EQ051);
_EQ051 = !bego
# over;
-- Node name is '|zonghejishu:u1|:73'
-- Equation name is '_LC8_F13', type is buried
_LC8_F13 = LCELL( _EQ052);
_EQ052 = _LC6_F13 & _LC7_F13;
Project Information e:\bahe1\yima\hexin.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,208K
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