📄 hexin.rpt
字号:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\bahe1\yima\hexin.rpt
hexin
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - F 21 OR2 ! 0 4 0 4 |yima:g1|:785
- 3 - F 19 OR2 ! 0 4 0 3 |yima:g1|:797
- 1 - F 19 OR2 ! 0 4 0 6 |yima:g1|:809
- 2 - F 19 OR2 ! 0 4 0 6 |yima:g1|:821
- 4 - F 19 AND2 0 4 0 3 |yima:g1|:833
- 7 - F 21 AND2 0 4 0 2 |yima:g1|:850
- 1 - F 22 OR2 s 0 3 0 5 |yima:g1|~857~1
- 4 - F 22 OR2 ! 0 2 0 1 |yima:g1|:857
- 3 - F 22 OR2 ! 0 4 0 4 |yima:g1|:869
- 6 - F 17 OR2 ! 0 4 0 4 |yima:g1|:881
- 4 - F 17 OR2 ! 0 4 0 4 |yima:g1|:893
- 6 - F 19 OR2 ! 0 4 0 4 |yima:g1|:905
- 8 - F 17 OR2 ! 0 4 0 3 |yima:g1|:917
- 4 - F 24 AND2 s 0 3 0 3 |yima:g1|~934~1
- 1 - F 24 AND2 s 0 4 0 3 |yima:g1|~934~2
- 6 - F 21 OR2 0 4 1 0 |yima:g1|:934
- 2 - F 22 OR2 0 4 1 0 |yima:g1|:982
- 2 - F 21 OR2 0 4 0 3 |yima:g1|:1015
- 8 - F 24 OR2 0 4 1 0 |yima:g1|:1030
- 3 - F 24 OR2 0 4 1 0 |yima:g1|:1078
- 7 - F 24 AND2 0 3 0 3 |yima:g1|:1117
- 6 - F 24 OR2 0 4 1 0 |yima:g1|:1126
- 5 - F 24 OR2 0 4 1 0 |yima:g1|:1174
- 2 - F 24 AND2 0 3 0 2 |yima:g1|:1219
- 3 - F 17 OR2 0 4 1 0 |yima:g1|:1222
- 2 - F 17 OR2 0 4 1 0 |yima:g1|:1268
- 8 - F 21 OR2 0 4 1 0 |yima:g1|:1318
- 5 - F 21 OR2 0 4 1 0 |yima:g1|:1366
- 4 - F 21 OR2 0 3 0 1 |yima:g1|:1378
- 2 - F 14 AND2 s 0 4 0 3 |yima:g1|~1414~1
- 3 - F 21 OR2 0 3 1 0 |yima:g1|:1414
- 3 - F 14 OR2 0 4 0 2 |yima:g1|:1429
- 1 - F 14 OR2 0 4 1 0 |yima:g1|:1462
- 6 - F 14 AND2 0 2 0 4 |yima:g1|:1480
- 7 - F 19 OR2 s 0 3 0 1 |yima:g1|~1510~1
- 8 - F 14 AND2 s 0 2 0 1 |yima:g1|~1510~2
- 7 - F 14 OR2 0 4 1 0 |yima:g1|:1510
- 8 - F 19 AND2 0 2 0 1 |yima:g1|:1531
- 4 - F 14 OR2 s 0 4 0 4 |yima:g1|~1558~1
- 5 - F 14 OR2 0 4 1 0 |yima:g1|:1558
- 5 - F 17 OR2 s 0 3 0 3 |yima:g1|~1606~1
- 5 - F 19 OR2 0 4 1 0 |yima:g1|:1606
- 6 - F 13 DFFE 5 0 0 1 |zonghejishu:u1|dchufa:i1|:3
- 1 - F 17 AND2 0 3 0 8 |zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:58|addcore:adder|:59
- 7 - F 17 OR2 0 3 0 4 |zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|pcarry2
- 4 - F 13 DFFE 1 4 0 23 |zonghejishu:u1|jishu16:g1|temp3 (|zonghejishu:u1|jishu16:g1|:8)
- 3 - F 13 DFFE 1 4 0 14 |zonghejishu:u1|jishu16:g1|temp2 (|zonghejishu:u1|jishu16:g1|:9)
- 2 - F 13 DFFE 1 3 0 15 |zonghejishu:u1|jishu16:g1|temp1 (|zonghejishu:u1|jishu16:g1|:10)
- 1 - F 13 DFFE 1 1 0 16 |zonghejishu:u1|jishu16:g1|temp0 (|zonghejishu:u1|jishu16:g1|:11)
- 5 - F 13 DFFE 3 1 0 3 |zonghejishu:u1|jkslect:u1|jout (|zonghejishu:u1|jkslect:u1|:5)
- 7 - F 13 OR2 4 0 0 1 |zonghejishu:u1|:58
- 2 - F 15 OR2 s 2 0 0 1 |zonghejishu:u1|~72~1
- 8 - F 13 AND2 0 2 0 4 |zonghejishu:u1|:73
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bahe1\yima\hexin.rpt
hexin
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 4/ 48( 8%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
F: 13/ 96( 13%) 0/ 48( 0%) 25/ 48( 52%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bahe1\yima\hexin.rpt
hexin
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 4 |zonghejishu:u1|:73
INPUT 2 cp
Device-Specific Information: e:\bahe1\yima\hexin.rpt
hexin
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clear
Device-Specific Information: e:\bahe1\yima\hexin.rpt
hexin
** EQUATIONS **
bego : INPUT;
clear : INPUT;
cp : INPUT;
left : INPUT;
over : INPUT;
right : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC5_F19;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC5_F14;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC7_F14;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC1_F14;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC3_F21;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC5_F21;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC8_F21;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = _LC2_F17;
-- Node name is 'q8'
-- Equation name is 'q8', type is output
q8 = _LC3_F17;
-- Node name is 'q9'
-- Equation name is 'q9', type is output
q9 = _LC5_F24;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = _LC6_F24;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = _LC3_F24;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = _LC8_F24;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = _LC2_F22;
-- Node name is 'q14'
-- Equation name is 'q14', type is output
q14 = _LC6_F21;
-- Node name is '|yima:g1|:785'
-- Equation name is '_LC1_F21', type is buried
!_LC1_F21 = _LC1_F21~NOT;
_LC1_F21~NOT = LCELL( _EQ001);
_EQ001 = !_LC1_F13
# _LC2_F13
# !_LC3_F13
# !_LC4_F13;
-- Node name is '|yima:g1|:797'
-- Equation name is '_LC3_F19', type is buried
!_LC3_F19 = _LC3_F19~NOT;
_LC3_F19~NOT = LCELL( _EQ002);
_EQ002 = _LC1_F13
# _LC2_F13
# !_LC3_F13
# !_LC4_F13;
-- Node name is '|yima:g1|:809'
-- Equation name is '_LC1_F19', type is buried
!_LC1_F19 = _LC1_F19~NOT;
_LC1_F19~NOT = LCELL( _EQ003);
_EQ003 = !_LC1_F13
# !_LC2_F13
# _LC3_F13
# !_LC4_F13;
-- Node name is '|yima:g1|:821'
-- Equation name is '_LC2_F19', type is buried
!_LC2_F19 = _LC2_F19~NOT;
_LC2_F19~NOT = LCELL( _EQ004);
_EQ004 = _LC1_F13
# !_LC2_F13
# _LC3_F13
# !_LC4_F13;
-- Node name is '|yima:g1|:833'
-- Equation name is '_LC4_F19', type is buried
_LC4_F19 = LCELL( _EQ005);
_EQ005 = _LC1_F13 & !_LC2_F13 & !_LC3_F13 & _LC4_F13;
-- Node name is '|yima:g1|:850'
-- Equation name is '_LC7_F21', type is buried
_LC7_F21 = LCELL( _EQ006);
_EQ006 = !_LC1_F19 & !_LC2_F19 & !_LC4_F19 & _LC6_F14;
-- Node name is '|yima:g1|~857~1'
-- Equation name is '_LC1_F22', type is buried
-- synthesized logic cell
_LC1_F22 = LCELL( _EQ007);
_EQ007 = _LC1_F13
# !_LC2_F13
# !_LC3_F13;
-- Node name is '|yima:g1|:857'
-- Equation name is '_LC4_F22', type is buried
!_LC4_F22 = _LC4_F22~NOT;
_LC4_F22~NOT = LCELL( _EQ008);
_EQ008 = _LC1_F22
# _LC4_F13;
-- Node name is '|yima:g1|:869'
-- Equation name is '_LC3_F22', type is buried
!_LC3_F22 = _LC3_F22~NOT;
_LC3_F22~NOT = LCELL( _EQ009);
_EQ009 = !_LC1_F13
# _LC2_F13
# !_LC3_F13
# _LC4_F13;
-- Node name is '|yima:g1|:881'
-- Equation name is '_LC6_F17', type is buried
!_LC6_F17 = _LC6_F17~NOT;
_LC6_F17~NOT = LCELL( _EQ010);
_EQ010 = _LC1_F13
# _LC2_F13
# !_LC3_F13
# _LC4_F13;
-- Node name is '|yima:g1|:893'
-- Equation name is '_LC4_F17', type is buried
!_LC4_F17 = _LC4_F17~NOT;
_LC4_F17~NOT = LCELL( _EQ011);
_EQ011 = !_LC1_F13
# !_LC2_F13
# _LC3_F13
# _LC4_F13;
-- Node name is '|yima:g1|:905'
-- Equation name is '_LC6_F19', type is buried
!_LC6_F19 = _LC6_F19~NOT;
_LC6_F19~NOT = LCELL( _EQ012);
_EQ012 = _LC1_F13
# !_LC2_F13
# _LC3_F13
# _LC4_F13;
-- Node name is '|yima:g1|:917'
-- Equation name is '_LC8_F17', type is buried
!_LC8_F17 = _LC8_F17~NOT;
_LC8_F17~NOT = LCELL( _EQ013);
_EQ013 = !_LC1_F13
# _LC2_F13
# _LC3_F13
# _LC4_F13;
-- Node name is '|yima:g1|~934~1'
-- Equation name is '_LC4_F24', type is buried
-- synthesized logic cell
_LC4_F24 = LCELL( _EQ014);
_EQ014 = !_LC4_F17 & _LC5_F17 & !_LC6_F19;
-- Node name is '|yima:g1|~934~2'
-- Equation name is '_LC1_F24', type is buried
-- synthesized logic cell
_LC1_F24 = LCELL( _EQ015);
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