📄 sum_cash.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity sum_cash is
port(clk : in std_logic;
rst : in std_logic;
c10 : in std_logic;
c50 : in std_logic;
c100: in std_logic;
lock_out_entry: in std_logic;
clear: in std_logic;
rc10 : in std_logic;
rc50 : in std_logic;
rc100: in std_logic;
sum : out integer range 0 to 20;
sum_10 : inout integer range -10 to 15;
sum_50 : inout integer range -10 to 15;
sum_100 : inout integer range -10 to 15);
end sum_cash;
architecture behavioral of sum_cash is
begin
sum_cash: process(rst,clk)
variable x: integer range 0 to 20;
begin
x:=sum_10+5*sum_50+10*sum_100;
if (x<21) then
sum <=x;
else
sum <=20;
end if;
if (rst='1')then
sum_10<=0;
sum_50<=0;
sum_100<=0;
sum<=0;
else
if (clear='1') then
sum_10<=0;
sum_50<=0;
sum_100<=0;
sum<=0;
end if;
--if clk'event and clk='1' then
if (lock_out_entry='0') then
if(c10='1') then
--sum_10<=0;
sum_10<=sum_10+1;
end if;
if(c50='1') then
sum_50<=sum_50+1;
end if;
if(c100='1') then
sum_100<=sum_100+1;
end if;
else
if (rc10='1') then
sum_10<=sum_10-1;
end if;
if (rc50='1') then
sum_50<=sum_50-1;
end if;
if (rc100='1') then
sum_100<=sum_100-1;
end if;
--end if;
end if;
end if;
end process;
end behavioral;
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