uart.txt

用FPGA实现了RS232异步串行通信

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity atel2_bin is
port( txclk: in std_logic;     						--2400Hz的波特率时钟
      reset: in std_logic;                    	--复位信号
       din: in std_logic_vector(15 downto 0);		--发送的数据
      start: in std_logic;        					--允许传输信号
       sout: out std_logic               		--串行输出端口
          ); 
end atel2_bin;
architecture behav of atel2_bin is
signal thr,len: std_logic_vector(15 downto 0);
signal txcnt_r: std_logic_vector(2 downto 0);
signal sout1: std_logic;
signal cou: integer:=0;
signal oddb:std_logic;
type s is(start1,start2,shift1,shift2,odd1,odd2,stop1,stop2);
signal state:s:=start1;   
begin
  process(txclk)      
    begin
      if rising_edge(txclk) then
           if cou<3 then thr<="0000000001010101";     --发送的文件头 
            elsif cou=3 then 
            thr<="0000000000000010";              --发送的文件长度
            elsif (cou>3 and state=stop2) then thr<=din;--发送的数据
            end if;   
      end if; 
  end process;
  process(reset,txclk)
  variable tsr,tsr1,oddb1,oddb2: std_logic_vector(7 downto 0);
   begin
         if reset='1' then 
            txcnt_r<=(others=>'0');
                 sout1<='1';
                    state<=start1;                     
                       cou<=0;
         elsif txclk'event and txclk='1' then                  
         case state is
         when start1=> 
              if start='1' then             
                 if cou=3 then
                    len<=thr;
                 end if;
                 tsr:=thr(7 downto 0);
				 oddb1:=thr(7 downto 0);  
                 sout1<='0'; --起始位  
                 txcnt_r<=(others=>'0');    
                 state<=shift1;
              else
                 state<=start1;
              end if;
         when shift1=>
              oddb<=oddb1(7) xor oddb1(6) xor oddb1(5) xor oddb1(4) xor oddb1(3) xor oddb1(2) xor oddb1(1) xor oddb1(0);
              sout1<=tsr(0); 					--数据位 
              tsr(6 downto 0):=tsr(7 downto 1);
              tsr(7):='0';
              txcnt_r<=txcnt_r+1;
              if (txcnt_r=7) then
                 state<=odd1;cou<=cou+1; 
              end if;
         when odd1=>         					--奇校验位
              if oddb='1' then
                 sout1<='0';state<=stop1;
              else
                 sout1<='1';state<=stop1;
              end if;
         when stop1=>
              sout1<='1';    --停止位
              if cou<4 then 
                 state<=start1;
              else
                 state<=start2;                              
              end if;
         when start2=> 
              tsr1:=thr(15 downto 8);
			  oddb2:=thr(15 downto 8);  
              sout1<='0';    				--起始位   
              txcnt_r<=(others=>'0');  
              state<=shift2;
         when shift2=>
              oddb<=oddb2(7) xor oddb2(6) xor oddb2(5) xor oddb2(4) xor oddb2(3) xor oddb2(2) xor oddb2(1) xor oddb2(0);
              sout1<=tsr1(0);				--数据位
              tsr1(6 downto 0):=tsr1(7 downto 1);
              tsr1(7):='0';
              txcnt_r<=txcnt_r+1;  
              if (txcnt_r=7) then
                 state<=odd2;                
              end if;
         when odd2=>       				--奇校验位
              if oddb='1' then
                 sout1<='0';state<=stop2;
              else
                 sout1<='1';state<=stop2;
              end if; 
         when stop2=>   
              sout1<='1';    				--停止位     
              if len="0000000000000000" then
                 state<=stop2;                  
              else
                 state<=start1;                
                 len<=len-1;
              end if;                         
         end case;
         end if;                 
   end process;  
  sout<=sout1;
end behav;