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📄 part5.fit.eqn

📁 基于FPGA的CPU设计 VHDL 编写
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--E1_q_b[0] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[0] at M4K_X26_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 8, Port B Depth: 32, Port B Width: 8
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[0] = E1_q_b[0]_PORT_B_data_out[0];

--E1_q_b[7] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[7] at M4K_X26_Y8
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[7] = E1_q_b[0]_PORT_B_data_out[7];

--E1_q_b[6] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[6] at M4K_X26_Y8
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[6] = E1_q_b[0]_PORT_B_data_out[6];

--E1_q_b[5] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[5] at M4K_X26_Y8
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[5] = E1_q_b[0]_PORT_B_data_out[5];

--E1_q_b[4] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4] at M4K_X26_Y8
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[4] = E1_q_b[0]_PORT_B_data_out[4];

--E1_q_b[3] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[3] at M4K_X26_Y8
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[3] = E1_q_b[0]_PORT_B_data_out[3];

--E1_q_b[2] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[2] at M4K_X26_Y8
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[2] = E1_q_b[0]_PORT_B_data_out[2];

--E1_q_b[1] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[1] at M4K_X26_Y8
E1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = GLOBAL(A1L2);
E1_q_b[0]_clock_1 = GLOBAL(A1L2);
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[1] = E1_q_b[0]_PORT_B_data_out[1];


--C2L1 is SEG7_LUT:u2|oSEG[0]~70 at LCCOMB_X27_Y1_N28
C2L1 = E1_q_b[2] & !E1_q_b[1] & (E1_q_b[0] $ !E1_q_b[3]) # !E1_q_b[2] & E1_q_b[0] & (E1_q_b[1] $ !E1_q_b[3]);


--C2L2 is SEG7_LUT:u2|oSEG[1]~71 at LCCOMB_X27_Y1_N10
C2L2 = E1_q_b[1] & (E1_q_b[0] & (E1_q_b[3]) # !E1_q_b[0] & E1_q_b[2]) # !E1_q_b[1] & E1_q_b[2] & (E1_q_b[0] $ E1_q_b[3]);


--C2L3 is SEG7_LUT:u2|oSEG[2]~72 at LCCOMB_X27_Y1_N4
C2L3 = E1_q_b[2] & E1_q_b[3] & (E1_q_b[1] # !E1_q_b[0]) # !E1_q_b[2] & E1_q_b[1] & !E1_q_b[0] & !E1_q_b[3];


--C2L4 is SEG7_LUT:u2|oSEG[3]~73 at LCCOMB_X27_Y1_N22
C2L4 = E1_q_b[0] & (E1_q_b[1] $ !E1_q_b[2]) # !E1_q_b[0] & (E1_q_b[1] & !E1_q_b[2] & E1_q_b[3] # !E1_q_b[1] & E1_q_b[2] & !E1_q_b[3]);


--C2L5 is SEG7_LUT:u2|oSEG[4]~74 at LCCOMB_X27_Y1_N12
C2L5 = E1_q_b[1] & (E1_q_b[0] & !E1_q_b[3]) # !E1_q_b[1] & (E1_q_b[2] & (!E1_q_b[3]) # !E1_q_b[2] & E1_q_b[0]);


--C2L6 is SEG7_LUT:u2|oSEG[5]~75 at LCCOMB_X27_Y1_N20
C2L6 = E1_q_b[1] & !E1_q_b[3] & (E1_q_b[0] # !E1_q_b[2]) # !E1_q_b[1] & E1_q_b[0] & (E1_q_b[2] $ !E1_q_b[3]);


--C2L7 is SEG7_LUT:u2|oSEG[6]~76 at LCCOMB_X27_Y1_N16
C2L7 = E1_q_b[0] & (E1_q_b[3] # E1_q_b[1] $ E1_q_b[2]) # !E1_q_b[0] & (E1_q_b[1] # E1_q_b[2] $ E1_q_b[3]);


--C1L1 is SEG7_LUT:u1|oSEG[0]~70 at LCCOMB_X64_Y5_N16
C1L1 = E1_q_b[7] & E1_q_b[4] & (E1_q_b[5] $ E1_q_b[6]) # !E1_q_b[7] & !E1_q_b[5] & (E1_q_b[4] $ E1_q_b[6]);


--C1L2 is SEG7_LUT:u1|oSEG[1]~71 at LCCOMB_X64_Y5_N8
C1L2 = E1_q_b[5] & (E1_q_b[4] & E1_q_b[7] # !E1_q_b[4] & (E1_q_b[6])) # !E1_q_b[5] & E1_q_b[6] & (E1_q_b[4] $ E1_q_b[7]);


--C1L3 is SEG7_LUT:u1|oSEG[2]~72 at LCCOMB_X64_Y5_N4
C1L3 = E1_q_b[7] & E1_q_b[6] & (E1_q_b[5] # !E1_q_b[4]) # !E1_q_b[7] & !E1_q_b[4] & E1_q_b[5] & !E1_q_b[6];


--C1L4 is SEG7_LUT:u1|oSEG[3]~73 at LCCOMB_X64_Y5_N18
C1L4 = E1_q_b[4] & (E1_q_b[5] $ (!E1_q_b[6])) # !E1_q_b[4] & (E1_q_b[5] & E1_q_b[7] & !E1_q_b[6] # !E1_q_b[5] & !E1_q_b[7] & E1_q_b[6]);


--C1L5 is SEG7_LUT:u1|oSEG[4]~74 at LCCOMB_X64_Y5_N12
C1L5 = E1_q_b[5] & E1_q_b[4] & !E1_q_b[7] # !E1_q_b[5] & (E1_q_b[6] & (!E1_q_b[7]) # !E1_q_b[6] & E1_q_b[4]);


--C1L6 is SEG7_LUT:u1|oSEG[5]~75 at LCCOMB_X64_Y5_N10
C1L6 = E1_q_b[4] & (E1_q_b[7] $ (E1_q_b[5] # !E1_q_b[6])) # !E1_q_b[4] & E1_q_b[5] & !E1_q_b[7] & !E1_q_b[6];


--C1L7 is SEG7_LUT:u1|oSEG[6]~76 at LCCOMB_X64_Y5_N6
C1L7 = E1_q_b[4] & (E1_q_b[7] # E1_q_b[5] $ E1_q_b[6]) # !E1_q_b[4] & (E1_q_b[5] # E1_q_b[7] $ E1_q_b[6]);


--read_addr[0] is read_addr[0] at LCFF_X64_Y8_N5
read_addr[0] = DFFEAS(A1L188, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--read_addr[1] is read_addr[1] at LCFF_X64_Y8_N7
read_addr[1] = DFFEAS(A1L191, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--read_addr[2] is read_addr[2] at LCFF_X64_Y8_N9
read_addr[2] = DFFEAS(A1L194, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--read_addr[3] is read_addr[3] at LCFF_X64_Y8_N11
read_addr[3] = DFFEAS(A1L197, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--C4L1 is SEG7_LUT:u4|oSEG[0]~70 at LCCOMB_X64_Y8_N22
C4L1 = read_addr[2] & !read_addr[1] & (read_addr[0] $ !read_addr[3]) # !read_addr[2] & read_addr[0] & (read_addr[1] $ !read_addr[3]);


--C4L2 is SEG7_LUT:u4|oSEG[1]~71 at LCCOMB_X64_Y8_N0
C4L2 = read_addr[1] & (read_addr[0] & (read_addr[3]) # !read_addr[0] & read_addr[2]) # !read_addr[1] & read_addr[2] & (read_addr[0] $ read_addr[3]);


--C4L3 is SEG7_LUT:u4|oSEG[2]~72 at LCCOMB_X64_Y8_N24
C4L3 = read_addr[2] & read_addr[3] & (read_addr[1] # !read_addr[0]) # !read_addr[2] & read_addr[1] & !read_addr[0] & !read_addr[3];


--C4L4 is SEG7_LUT:u4|oSEG[3]~73 at LCCOMB_X64_Y8_N18
C4L4 = read_addr[0] & (read_addr[1] $ !read_addr[2]) # !read_addr[0] & (read_addr[1] & !read_addr[2] & read_addr[3] # !read_addr[1] & read_addr[2] & !read_addr[3]);


--C4L5 is SEG7_LUT:u4|oSEG[4]~74 at LCCOMB_X64_Y8_N26
C4L5 = read_addr[1] & read_addr[0] & (!read_addr[3]) # !read_addr[1] & (read_addr[2] & (!read_addr[3]) # !read_addr[2] & read_addr[0]);


--C4L6 is SEG7_LUT:u4|oSEG[5]~75 at LCCOMB_X64_Y8_N28
C4L6 = read_addr[1] & !read_addr[3] & (read_addr[0] # !read_addr[2]) # !read_addr[1] & read_addr[0] & (read_addr[2] $ !read_addr[3]);


--C4L7 is SEG7_LUT:u4|oSEG[6]~76 at LCCOMB_X64_Y8_N16
C4L7 = read_addr[0] & (read_addr[3] # read_addr[1] $ read_addr[2]) # !read_addr[0] & (read_addr[1] # read_addr[2] $ read_addr[3]);


--read_addr[4] is read_addr[4] at LCFF_X64_Y8_N13
read_addr[4] = DFFEAS(A1L200, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--C6L1 is SEG7_LUT:u6|oSEG[0]~70 at LCCOMB_X1_Y13_N20
C6L1 = SW[2] & !SW[1] & (SW[0] $ !SW[3]) # !SW[2] & SW[0] & (SW[1] $ !SW[3]);


--C6L2 is SEG7_LUT:u6|oSEG[1]~71 at LCCOMB_X1_Y13_N10
C6L2 = SW[1] & (SW[0] & (SW[3]) # !SW[0] & SW[2]) # !SW[1] & SW[2] & (SW[0] $ SW[3]);


--C6L3 is SEG7_LUT:u6|oSEG[2]~72 at LCCOMB_X1_Y13_N28
C6L3 = SW[2] & SW[3] & (SW[1] # !SW[0]) # !SW[2] & !SW[0] & SW[1] & !SW[3];


--C6L4 is SEG7_LUT:u6|oSEG[3]~73 at LCCOMB_X1_Y13_N4
C6L4 = SW[0] & (SW[2] $ !SW[1]) # !SW[0] & (SW[2] & !SW[1] & !SW[3] # !SW[2] & SW[1] & SW[3]);


--C6L5 is SEG7_LUT:u6|oSEG[4]~74 at LCCOMB_X1_Y13_N26
C6L5 = SW[1] & (SW[0] & !SW[3]) # !SW[1] & (SW[2] & (!SW[3]) # !SW[2] & SW[0]);


--C6L6 is SEG7_LUT:u6|oSEG[5]~75 at LCCOMB_X1_Y13_N0
C6L6 = SW[2] & SW[0] & (SW[1] $ SW[3]) # !SW[2] & !SW[3] & (SW[0] # SW[1]);


--C6L7 is SEG7_LUT:u6|oSEG[6]~76 at LCCOMB_X1_Y13_N12
C6L7 = SW[0] & (SW[3] # SW[2] $ SW[1]) # !SW[0] & (SW[1] # SW[2] $ SW[3]);


--C5L1 is SEG7_LUT:u5|oSEG[0]~70 at LCCOMB_X1_Y15_N20
C5L1 = SW[6] & !SW[5] & (SW[4] $ !SW[7]) # !SW[6] & SW[4] & (SW[5] $ !SW[7]);


--C5L2 is SEG7_LUT:u5|oSEG[1]~71 at LCCOMB_X1_Y15_N12
C5L2 = SW[5] & (SW[4] & (SW[7]) # !SW[4] & SW[6]) # !SW[5] & SW[6] & (SW[4] $ SW[7]);


--C5L3 is SEG7_LUT:u5|oSEG[2]~72 at LCCOMB_X1_Y15_N28
C5L3 = SW[6] & SW[7] & (SW[5] # !SW[4]) # !SW[6] & SW[5] & !SW[4] & !SW[7];


--C5L4 is SEG7_LUT:u5|oSEG[3]~73 at LCCOMB_X1_Y15_N4
C5L4 = SW[4] & (SW[5] $ !SW[6]) # !SW[4] & (SW[5] & !SW[6] & SW[7] # !SW[5] & SW[6] & !SW[7]);


--C5L5 is SEG7_LUT:u5|oSEG[4]~74 at LCCOMB_X1_Y15_N26
C5L5 = SW[5] & (SW[4] & !SW[7]) # !SW[5] & (SW[6] & (!SW[7]) # !SW[6] & SW[4]);


--C5L6 is SEG7_LUT:u5|oSEG[5]~75 at LCCOMB_X1_Y15_N0
C5L6 = SW[5] & !SW[7] & (SW[4] # !SW[6]) # !SW[5] & SW[4] & (SW[6] $ !SW[7]);


--C5L7 is SEG7_LUT:u5|oSEG[6]~76 at LCCOMB_X1_Y15_N10
C5L7 = SW[4] & (SW[7] # SW[5] $ SW[6]) # !SW[4] & (SW[5] # SW[6] $ SW[7]);


--C8L1 is SEG7_LUT:u8|oSEG[0]~70 at LCCOMB_X1_Y17_N20
C8L1 = SW[13] & !SW[12] & (SW[11] $ !SW[14]) # !SW[13] & SW[11] & (SW[12] $ !SW[14]);


--C8L2 is SEG7_LUT:u8|oSEG[1]~71 at LCCOMB_X1_Y17_N10
C8L2 = SW[12] & (SW[11] & (SW[14]) # !SW[11] & SW[13]) # !SW[12] & SW[13] & (SW[11] $ SW[14]);


--C8L3 is SEG7_LUT:u8|oSEG[2]~72 at LCCOMB_X1_Y17_N28
C8L3 = SW[13] & SW[14] & (SW[12] # !SW[11]) # !SW[13] & SW[12] & !SW[11] & !SW[14];


--C8L4 is SEG7_LUT:u8|oSEG[3]~73 at LCCOMB_X1_Y17_N4
C8L4 = SW[11] & (SW[12] $ !SW[13]) # !SW[11] & (SW[12] & !SW[13] & SW[14] # !SW[12] & SW[13] & !SW[14]);


--C8L5 is SEG7_LUT:u8|oSEG[4]~74 at LCCOMB_X1_Y17_N26
C8L5 = SW[12] & (SW[11] & !SW[14]) # !SW[12] & (SW[13] & (!SW[14]) # !SW[13] & SW[11]);


--C8L6 is SEG7_LUT:u8|oSEG[5]~75 at LCCOMB_X1_Y17_N18
C8L6 = SW[12] & !SW[14] & (SW[11] # !SW[13]) # !SW[12] & SW[11] & (SW[13] $ !SW[14]);


--C8L7 is SEG7_LUT:u8|oSEG[6]~76 at LCCOMB_X1_Y17_N12
C8L7 = SW[11] & (SW[14] # SW[12] $ SW[13]) # !SW[11] & (SW[12] # SW[13] $ SW[14]);


--A1L188 is read_addr[0]~55 at LCCOMB_X64_Y8_N4
A1L188 = read_addr[0] $ VCC;

--A1L189 is read_addr[0]~56 at LCCOMB_X64_Y8_N4
A1L189 = CARRY(read_addr[0]);


--count[24] is count[24] at LCFF_X63_Y11_N23
count[24] = DFFEAS(A1L181, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[18] is count[18] at LCFF_X63_Y11_N11
count[18] = DFFEAS(A1L163, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[16] is count[16] at LCFF_X63_Y11_N7
count[16] = DFFEAS(A1L157, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--A1L81 is LessThan~398 at LCCOMB_X62_Y11_N4
A1L81 = !count[16] & !count[18] & !count[24];


--count[12] is count[12] at LCFF_X63_Y12_N31
count[12] = DFFEAS(A1L145, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[13] is count[13] at LCFF_X63_Y11_N1
count[13] = DFFEAS(A1L148, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[14] is count[14] at LCFF_X63_Y11_N3
count[14] = DFFEAS(A1L151, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[15] is count[15] at LCFF_X63_Y11_N5
count[15] = DFFEAS(A1L154, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--A1L82 is LessThan~399 at LCCOMB_X63_Y12_N4
A1L82 = !count[12] # !count[15] # !count[13] # !count[14];


--count[7] is count[7] at LCFF_X63_Y12_N21
count[7] = DFFEAS(A1L130, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[8] is count[8] at LCFF_X63_Y12_N23
count[8] = DFFEAS(A1L133, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[9] is count[9] at LCFF_X63_Y12_N25
count[9] = DFFEAS(A1L136, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--count[10] is count[10] at LCFF_X63_Y12_N27
count[10] = DFFEAS(A1L139, GLOBAL(A1L2), KEY[0],  ,  ,  ,  , A1L87,  );


--A1L83 is LessThan~400 at LCCOMB_X63_Y12_N2
A1L83 = !count[7] & !count[8] & !count[9] & !count[10];
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