part5.map.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 19 14:23:15 2007 " "Info: Processing started: Thu Apr 19 14:23:15 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part5.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file part5.v" { { "Info" "ISGN_ENTITY_NAME" "1 part5 " "Info: Found entity 1: part5" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part5 " "Info: Elaborating entity \"part5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 part5.v(28) " "Warning (10230): Verilog HDL assignment warning at part5.v(28): truncated value with size 32 to match size of target (26)" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 part5.v(33) " "Warning (10230): Verilog HDL assignment warning at part5.v(33): truncated value with size 32 to match size of target (5)" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[7\] part5.v(7) " "Warning (10034): Output port \"LEDG\[7\]\" at part5.v(7) has no driver" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[6\] part5.v(7) " "Warning (10034): Output port \"LEDG\[6\]\" at part5.v(7) has no driver" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[5\] part5.v(7) " "Warning (10034): Output port \"LEDG\[5\]\" at part5.v(7) has no driver" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[4\] part5.v(7) " "Warning (10034): Output port \"LEDG\[4\]\" at part5.v(7) has no driver" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[3\] part5.v(7) " "Warning (10034): Output port \"LEDG\[3\]\" at part5.v(7) has no driver" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[2\] part5.v(7) " "Warning (10034): Output port \"LEDG\[2\]\" at part5.v(7) has no driver" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[1\] part5.v(7) " "Warning (10034): Output port \"LEDG\[1\]\" at part5.v(7) has no driver" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ramlpm.v 1 1 " "Warning: Using design file ramlpm.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ramlpm " "Info: Found entity 1: ramlpm" {  } { { "ramlpm.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/ramlpm.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}