part5.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 HEX1\[1\] ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~portb_address_reg0 13.172 ns memory " "Info: tco from clock \"CLOCK_50\" to destination pin \"HEX1\[1\]\" through memory \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~portb_address_reg0\" is 13.172 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.754 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK_50\" to source memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 57 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 57; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.958 ns) + CELL(0.689 ns) 2.754 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X26_Y8 8 " "Info: 3: + IC(0.958 ns) + CELL(0.689 ns) = 2.754 ns; Loc. = M4K_X26_Y8; Fanout = 8; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.647 ns" { CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.678 ns ( 60.93 % ) " "Info: Total cell delay = 1.678 ns ( 60.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.076 ns ( 39.07 % ) " "Info: Total interconnect delay = 1.076 ns ( 39.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.754 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.754 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.118ns 0.958ns } { 0.000ns 0.989ns 0.000ns 0.689ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.209 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.209 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M4K_X26_Y8 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y8; Fanout = 8; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.991 ns) 2.991 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|q_b\[4\] 2 MEM M4K_X26_Y8 7 " "Info: 2: + IC(0.000 ns) + CELL(2.991 ns) = 2.991 ns; Loc. = M4K_X26_Y8; Fanout = 7; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|q_b\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.991 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4] } "NODE_NAME" } "" } } { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.251 ns) + CELL(0.437 ns) 6.679 ns SEG7_LUT:u1\|oSEG\[1\]~71 3 COMB LCCOMB_X64_Y5_N8 1 " "Info: 3: + IC(3.251 ns) + CELL(0.437 ns) = 6.679 ns; Loc. = LCCOMB_X64_Y5_N8; Fanout = 1; COMB Node = 'SEG7_LUT:u1\|oSEG\[1\]~71'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "3.688 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4] SEG7_LUT:u1|oSEG[1]~71 } "NODE_NAME" } "" } } { "SEG7_LUT.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/SEG7_LUT.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(2.779 ns) 10.209 ns HEX1\[1\] 4 PIN PIN_V21 0 " "Info: 4: + IC(0.751 ns) + CELL(2.779 ns) = 10.209 ns; Loc. = PIN_V21; Fanout = 0; PIN Node = 'HEX1\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "3.530 ns" { SEG7_LUT:u1|oSEG[1]~71 HEX1[1] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.207 ns ( 60.80 % ) " "Info: Total cell delay = 6.207 ns ( 60.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.002 ns ( 39.20 % ) " "Info: Total interconnect delay = 4.002 ns ( 39.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "10.209 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4] SEG7_LUT:u1|oSEG[1]~71 HEX1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.209 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4] SEG7_LUT:u1|oSEG[1]~71 HEX1[1] } { 0.000ns 0.000ns 3.251ns 0.751ns } { 0.000ns 2.991ns 0.437ns 2.779ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.754 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.754 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.118ns 0.958ns } { 0.000ns 0.989ns 0.000ns 0.689ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "10.209 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4] SEG7_LUT:u1|oSEG[1]~71 HEX1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.209 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg0 ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4] SEG7_LUT:u1|oSEG[1]~71 HEX1[1] } { 0.000ns 0.000ns 3.251ns 0.751ns } { 0.000ns 2.991ns 0.437ns 2.779ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[17\] LEDG\[0\] 10.087 ns Longest " "Info: Longest tpd from source pin \"SW\[17\]\" to destination pin \"LEDG\[0\]\" is 10.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[17\] 1 PIN PIN_V2 14 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 14; PIN Node = 'SW\[17\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { SW[17] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.437 ns) + CELL(2.798 ns) 10.087 ns LEDG\[0\] 2 PIN PIN_AE22 0 " "Info: 2: + IC(6.437 ns) + CELL(2.798 ns) = 10.087 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'LEDG\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "9.235 ns" { SW[17] LEDG[0] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.650 ns ( 36.19 % ) " "Info: Total cell delay = 3.650 ns ( 36.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.437 ns ( 63.81 % ) " "Info: Total interconnect delay = 6.437 ns ( 63.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "10.087 ns" { SW[17] LEDG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.087 ns" { SW[17] SW[17]~combout LEDG[0] } { 0.000ns 0.000ns 6.437ns } { 0.000ns 0.852ns 2.798ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg4 SW\[4\] CLOCK_50 0.359 ns memory " "Info: th for memory \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg4\" (data pin = \"SW\[4\]\", clock pin = \"CLOCK_50\") is 0.359 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.725 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK_50\" to destination memory is 2.725 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 57 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 57; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.958 ns) + CELL(0.660 ns) 2.725 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg4 3 MEM M4K_X26_Y8 1 " "Info: 3: + IC(0.958 ns) + CELL(0.660 ns) = 2.725 ns; Loc. = M4K_X26_Y8; Fanout = 1; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.618 ns" { CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.649 ns ( 60.51 % ) " "Info: Total cell delay = 1.649 ns ( 60.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.076 ns ( 39.49 % ) " "Info: Total interconnect delay = 1.076 ns ( 39.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.725 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.725 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } { 0.000ns 0.000ns 0.118ns 0.958ns } { 0.000ns 0.989ns 0.000ns 0.660ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.234 ns + " "Info: + Micro hold delay of destination is 0.234 ns" {  } { { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.600 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns SW\[4\] 1 PIN PIN_AF14 8 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AF14; Fanout = 8; PIN Node = 'SW\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { SW[4] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.106 ns) 2.600 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg4 2 MEM M4K_X26_Y8 1 " "Info: 2: + IC(1.505 ns) + CELL(0.106 ns) = 2.600 ns; Loc. = M4K_X26_Y8; Fanout = 1; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.611 ns" { SW[4] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.095 ns ( 42.12 % ) " "Info: Total cell delay = 1.095 ns ( 42.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns ( 57.88 % ) " "Info: Total interconnect delay = 1.505 ns ( 57.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.600 ns" { SW[4] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.600 ns" { SW[4] SW[4]~combout ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } { 0.000ns 0.000ns 1.505ns } { 0.000ns 0.989ns 0.106ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.725 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.725 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } { 0.000ns 0.000ns 0.118ns 0.958ns } { 0.000ns 0.989ns 0.000ns 0.660ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.600 ns" { SW[4] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.600 ns" { SW[4] SW[4]~combout ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4 } { 0.000ns 0.000ns 1.505ns } { 0.000ns 0.989ns 0.106ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}