part5.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register count\[14\] register read_addr\[4\] 216.59 MHz 4.617 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 216.59 MHz between source register \"count\[14\]\" and destination register \"read_addr\[4\]\" (period= 4.617 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.414 ns + Longest register register " "Info: + Longest register to register delay is 4.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[14\] 1 REG LCFF_X63_Y11_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y11_N3; Fanout = 3; REG Node = 'count\[14\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { count[14] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.438 ns) 1.227 ns LessThan~399 2 COMB LCCOMB_X63_Y12_N4 1 " "Info: 2: + IC(0.789 ns) + CELL(0.438 ns) = 1.227 ns; Loc. = LCCOMB_X63_Y12_N4; Fanout = 1; COMB Node = 'LessThan~399'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.227 ns" { count[14] LessThan~399 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.437 ns) 2.398 ns LessThan~401 3 COMB LCCOMB_X63_Y11_N28 1 " "Info: 3: + IC(0.734 ns) + CELL(0.437 ns) = 2.398 ns; Loc. = LCCOMB_X63_Y11_N28; Fanout = 1; COMB Node = 'LessThan~401'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.171 ns" { LessThan~399 LessThan~401 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.252 ns) + CELL(0.378 ns) 3.028 ns LessThan~404 4 COMB LCCOMB_X63_Y11_N26 31 " "Info: 4: + IC(0.252 ns) + CELL(0.378 ns) = 3.028 ns; Loc. = LCCOMB_X63_Y11_N26; Fanout = 31; COMB Node = 'LessThan~404'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "0.630 ns" { LessThan~401 LessThan~404 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.726 ns) + CELL(0.660 ns) 4.414 ns read_addr\[4\] 5 REG LCFF_X64_Y8_N13 6 " "Info: 5: + IC(0.726 ns) + CELL(0.660 ns) = 4.414 ns; Loc. = LCFF_X64_Y8_N13; Fanout = 6; REG Node = 'read_addr\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.386 ns" { LessThan~404 read_addr[4] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.913 ns ( 43.34 % ) " "Info: Total cell delay = 1.913 ns ( 43.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.501 ns ( 56.66 % ) " "Info: Total interconnect delay = 2.501 ns ( 56.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "4.414 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.414 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } { 0.000ns 0.789ns 0.734ns 0.252ns 0.726ns } { 0.000ns 0.438ns 0.437ns 0.378ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.011 ns - Smallest " "Info: - Smallest clock skew is 0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.661 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 57 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 57; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 2.661 ns read_addr\[4\] 3 REG LCFF_X64_Y8_N13 6 " "Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.661 ns; Loc. = LCFF_X64_Y8_N13; Fanout = 6; REG Node = 'read_addr\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.554 ns" { CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 57.35 % ) " "Info: Total cell delay = 1.526 ns ( 57.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.135 ns ( 42.65 % ) " "Info: Total interconnect delay = 1.135 ns ( 42.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.661 ns" { CLOCK_50 CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.661 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl read_addr[4] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.650 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 57 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 57; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.537 ns) 2.650 ns count\[14\] 3 REG LCFF_X63_Y11_N3 3 " "Info: 3: + IC(1.006 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X63_Y11_N3; Fanout = 3; REG Node = 'count\[14\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.543 ns" { CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 57.58 % ) " "Info: Total cell delay = 1.526 ns ( 57.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.124 ns ( 42.42 % ) " "Info: Total interconnect delay = 1.124 ns ( 42.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.650 ns" { CLOCK_50 CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.650 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl count[14] } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.661 ns" { CLOCK_50 CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.661 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl read_addr[4] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.650 ns" { CLOCK_50 CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.650 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl count[14] } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "4.414 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.414 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } { 0.000ns 0.789ns 0.734ns 0.252ns 0.726ns } { 0.000ns 0.438ns 0.437ns 0.378ns 0.660ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.661 ns" { CLOCK_50 CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.661 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl read_addr[4] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.650 ns" { CLOCK_50 CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.650 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl count[14] } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg0 SW\[17\] CLOCK_50 4.324 ns memory " "Info: tsu for memory \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg0\" (data pin = \"SW\[17\]\", clock pin = \"CLOCK_50\") is 4.324 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.014 ns + Longest pin memory " "Info: + Longest pin to memory delay is 7.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[17\] 1 PIN PIN_V2 14 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 14; PIN Node = 'SW\[17\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { SW[17] } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.531 ns) + CELL(0.631 ns) 7.014 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg0 2 MEM M4K_X26_Y8 1 " "Info: 2: + IC(5.531 ns) + CELL(0.631 ns) = 7.014 ns; Loc. = M4K_X26_Y8; Fanout = 1; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "6.162 ns" { SW[17] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.483 ns ( 21.14 % ) " "Info: Total cell delay = 1.483 ns ( 21.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.531 ns ( 78.86 % ) " "Info: Total interconnect delay = 5.531 ns ( 78.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "7.014 ns" { SW[17] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.014 ns" { SW[17] SW[17]~combout ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 5.531ns } { 0.000ns 0.852ns 0.631ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.725 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination memory is 2.725 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 57 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 57; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part5.v" "" { Text "C:/altera/quartus51/exercise/lab8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.958 ns) + CELL(0.660 ns) 2.725 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg0 3 MEM M4K_X26_Y8 1 " "Info: 3: + IC(0.958 ns) + CELL(0.660 ns) = 2.725 ns; Loc. = M4K_X26_Y8; Fanout = 1; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_1qi1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "1.618 ns" { CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1qi1.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part5/db/altsyncram_1qi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.649 ns ( 60.51 % ) " "Info: Total cell delay = 1.649 ns ( 60.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.076 ns ( 39.49 % ) " "Info: Total interconnect delay = 1.076 ns ( 39.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.725 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.725 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.118ns 0.958ns } { 0.000ns 0.989ns 0.000ns 0.660ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "7.014 ns" { SW[17] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.014 ns" { SW[17] SW[17]~combout ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 5.531ns } { 0.000ns 0.852ns 0.631ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part5" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part5/db/part5.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part5/" "" "2.725 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.725 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.118ns 0.958ns } { 0.000ns 0.989ns 0.000ns 0.660ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}