part5.map.eqn

基于FPGA的CPU设计 VHDL 编写

-- Copyright (C) 1991-2005 Altera Corporation
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--E1_q_b[0] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[0]_PORT_A_data_in = SW[0];
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = VCC;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , E1_q_b[0]_clock_enable_0);
E1_q_b[0]_PORT_B_read_enable = VCC;
E1_q_b[0]_PORT_B_read_enable_reg = DFFE(E1_q_b[0]_PORT_B_read_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = CLOCK_50;
E1_q_b[0]_clock_1 = CLOCK_50;
E1_q_b[0]_clock_enable_0 = SW[17];
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, , E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_read_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, E1_q_b[0]_clock_enable_0, , , );
E1_q_b[0] = E1_q_b[0]_PORT_B_data_out[0];


--E1_q_b[1] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[1]_PORT_A_data_in = SW[1];
E1_q_b[1]_PORT_A_data_in_reg = DFFE(E1_q_b[1]_PORT_A_data_in, E1_q_b[1]_clock_0, , , E1_q_b[1]_clock_enable_0);
E1_q_b[1]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[1]_PORT_A_address_reg = DFFE(E1_q_b[1]_PORT_A_address, E1_q_b[1]_clock_0, , , E1_q_b[1]_clock_enable_0);
E1_q_b[1]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[1]_PORT_B_address_reg = DFFE(E1_q_b[1]_PORT_B_address, E1_q_b[1]_clock_1, , , );
E1_q_b[1]_PORT_A_write_enable = VCC;
E1_q_b[1]_PORT_A_write_enable_reg = DFFE(E1_q_b[1]_PORT_A_write_enable, E1_q_b[1]_clock_0, , , E1_q_b[1]_clock_enable_0);
E1_q_b[1]_PORT_B_read_enable = VCC;
E1_q_b[1]_PORT_B_read_enable_reg = DFFE(E1_q_b[1]_PORT_B_read_enable, E1_q_b[1]_clock_1, , , );
E1_q_b[1]_clock_0 = CLOCK_50;
E1_q_b[1]_clock_1 = CLOCK_50;
E1_q_b[1]_clock_enable_0 = SW[17];
E1_q_b[1]_PORT_B_data_out = MEMORY(E1_q_b[1]_PORT_A_data_in_reg, , E1_q_b[1]_PORT_A_address_reg, E1_q_b[1]_PORT_B_address_reg, E1_q_b[1]_PORT_A_write_enable_reg, E1_q_b[1]_PORT_B_read_enable_reg, , , E1_q_b[1]_clock_0, E1_q_b[1]_clock_1, E1_q_b[1]_clock_enable_0, , , );
E1_q_b[1] = E1_q_b[1]_PORT_B_data_out[0];


--E1_q_b[2] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[2]_PORT_A_data_in = SW[2];
E1_q_b[2]_PORT_A_data_in_reg = DFFE(E1_q_b[2]_PORT_A_data_in, E1_q_b[2]_clock_0, , , E1_q_b[2]_clock_enable_0);
E1_q_b[2]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[2]_PORT_A_address_reg = DFFE(E1_q_b[2]_PORT_A_address, E1_q_b[2]_clock_0, , , E1_q_b[2]_clock_enable_0);
E1_q_b[2]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[2]_PORT_B_address_reg = DFFE(E1_q_b[2]_PORT_B_address, E1_q_b[2]_clock_1, , , );
E1_q_b[2]_PORT_A_write_enable = VCC;
E1_q_b[2]_PORT_A_write_enable_reg = DFFE(E1_q_b[2]_PORT_A_write_enable, E1_q_b[2]_clock_0, , , E1_q_b[2]_clock_enable_0);
E1_q_b[2]_PORT_B_read_enable = VCC;
E1_q_b[2]_PORT_B_read_enable_reg = DFFE(E1_q_b[2]_PORT_B_read_enable, E1_q_b[2]_clock_1, , , );
E1_q_b[2]_clock_0 = CLOCK_50;
E1_q_b[2]_clock_1 = CLOCK_50;
E1_q_b[2]_clock_enable_0 = SW[17];
E1_q_b[2]_PORT_B_data_out = MEMORY(E1_q_b[2]_PORT_A_data_in_reg, , E1_q_b[2]_PORT_A_address_reg, E1_q_b[2]_PORT_B_address_reg, E1_q_b[2]_PORT_A_write_enable_reg, E1_q_b[2]_PORT_B_read_enable_reg, , , E1_q_b[2]_clock_0, E1_q_b[2]_clock_1, E1_q_b[2]_clock_enable_0, , , );
E1_q_b[2] = E1_q_b[2]_PORT_B_data_out[0];


--E1_q_b[3] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[3]_PORT_A_data_in = SW[3];
E1_q_b[3]_PORT_A_data_in_reg = DFFE(E1_q_b[3]_PORT_A_data_in, E1_q_b[3]_clock_0, , , E1_q_b[3]_clock_enable_0);
E1_q_b[3]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[3]_PORT_A_address_reg = DFFE(E1_q_b[3]_PORT_A_address, E1_q_b[3]_clock_0, , , E1_q_b[3]_clock_enable_0);
E1_q_b[3]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[3]_PORT_B_address_reg = DFFE(E1_q_b[3]_PORT_B_address, E1_q_b[3]_clock_1, , , );
E1_q_b[3]_PORT_A_write_enable = VCC;
E1_q_b[3]_PORT_A_write_enable_reg = DFFE(E1_q_b[3]_PORT_A_write_enable, E1_q_b[3]_clock_0, , , E1_q_b[3]_clock_enable_0);
E1_q_b[3]_PORT_B_read_enable = VCC;
E1_q_b[3]_PORT_B_read_enable_reg = DFFE(E1_q_b[3]_PORT_B_read_enable, E1_q_b[3]_clock_1, , , );
E1_q_b[3]_clock_0 = CLOCK_50;
E1_q_b[3]_clock_1 = CLOCK_50;
E1_q_b[3]_clock_enable_0 = SW[17];
E1_q_b[3]_PORT_B_data_out = MEMORY(E1_q_b[3]_PORT_A_data_in_reg, , E1_q_b[3]_PORT_A_address_reg, E1_q_b[3]_PORT_B_address_reg, E1_q_b[3]_PORT_A_write_enable_reg, E1_q_b[3]_PORT_B_read_enable_reg, , , E1_q_b[3]_clock_0, E1_q_b[3]_clock_1, E1_q_b[3]_clock_enable_0, , , );
E1_q_b[3] = E1_q_b[3]_PORT_B_data_out[0];


--C2L1 is SEG7_LUT:u2|oSEG[0]~70
C2L1 = E1_q_b[2] & !E1_q_b[1] & (E1_q_b[0] $ !E1_q_b[3]) # !E1_q_b[2] & E1_q_b[0] & (E1_q_b[1] $ !E1_q_b[3]);


--C2L2 is SEG7_LUT:u2|oSEG[1]~71
C2L2 = E1_q_b[1] & (E1_q_b[0] & (E1_q_b[3]) # !E1_q_b[0] & E1_q_b[2]) # !E1_q_b[1] & E1_q_b[2] & (E1_q_b[0] $ E1_q_b[3]);


--C2L3 is SEG7_LUT:u2|oSEG[2]~72
C2L3 = E1_q_b[2] & E1_q_b[3] & (E1_q_b[1] # !E1_q_b[0]) # !E1_q_b[2] & !E1_q_b[0] & E1_q_b[1] & !E1_q_b[3];


--C2L4 is SEG7_LUT:u2|oSEG[3]~73
C2L4 = E1_q_b[0] & (E1_q_b[1] $ !E1_q_b[2]) # !E1_q_b[0] & (E1_q_b[1] & !E1_q_b[2] & E1_q_b[3] # !E1_q_b[1] & E1_q_b[2] & !E1_q_b[3]);


--C2L5 is SEG7_LUT:u2|oSEG[4]~74
C2L5 = E1_q_b[1] & E1_q_b[0] & (!E1_q_b[3]) # !E1_q_b[1] & (E1_q_b[2] & (!E1_q_b[3]) # !E1_q_b[2] & E1_q_b[0]);


--C2L6 is SEG7_LUT:u2|oSEG[5]~75
C2L6 = E1_q_b[0] & (E1_q_b[3] $ (E1_q_b[1] # !E1_q_b[2])) # !E1_q_b[0] & E1_q_b[1] & !E1_q_b[2] & !E1_q_b[3];


--C2L7 is SEG7_LUT:u2|oSEG[6]~76
C2L7 = E1_q_b[0] & (E1_q_b[3] # E1_q_b[1] $ E1_q_b[2]) # !E1_q_b[0] & (E1_q_b[1] # E1_q_b[2] $ E1_q_b[3]);


--E1_q_b[4] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[4]_PORT_A_data_in = SW[4];
E1_q_b[4]_PORT_A_data_in_reg = DFFE(E1_q_b[4]_PORT_A_data_in, E1_q_b[4]_clock_0, , , E1_q_b[4]_clock_enable_0);
E1_q_b[4]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[4]_PORT_A_address_reg = DFFE(E1_q_b[4]_PORT_A_address, E1_q_b[4]_clock_0, , , E1_q_b[4]_clock_enable_0);
E1_q_b[4]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[4]_PORT_B_address_reg = DFFE(E1_q_b[4]_PORT_B_address, E1_q_b[4]_clock_1, , , );
E1_q_b[4]_PORT_A_write_enable = VCC;
E1_q_b[4]_PORT_A_write_enable_reg = DFFE(E1_q_b[4]_PORT_A_write_enable, E1_q_b[4]_clock_0, , , E1_q_b[4]_clock_enable_0);
E1_q_b[4]_PORT_B_read_enable = VCC;
E1_q_b[4]_PORT_B_read_enable_reg = DFFE(E1_q_b[4]_PORT_B_read_enable, E1_q_b[4]_clock_1, , , );
E1_q_b[4]_clock_0 = CLOCK_50;
E1_q_b[4]_clock_1 = CLOCK_50;
E1_q_b[4]_clock_enable_0 = SW[17];
E1_q_b[4]_PORT_B_data_out = MEMORY(E1_q_b[4]_PORT_A_data_in_reg, , E1_q_b[4]_PORT_A_address_reg, E1_q_b[4]_PORT_B_address_reg, E1_q_b[4]_PORT_A_write_enable_reg, E1_q_b[4]_PORT_B_read_enable_reg, , , E1_q_b[4]_clock_0, E1_q_b[4]_clock_1, E1_q_b[4]_clock_enable_0, , , );
E1_q_b[4] = E1_q_b[4]_PORT_B_data_out[0];


--E1_q_b[5] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[5]_PORT_A_data_in = SW[5];
E1_q_b[5]_PORT_A_data_in_reg = DFFE(E1_q_b[5]_PORT_A_data_in, E1_q_b[5]_clock_0, , , E1_q_b[5]_clock_enable_0);
E1_q_b[5]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[5]_PORT_A_address_reg = DFFE(E1_q_b[5]_PORT_A_address, E1_q_b[5]_clock_0, , , E1_q_b[5]_clock_enable_0);
E1_q_b[5]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[5]_PORT_B_address_reg = DFFE(E1_q_b[5]_PORT_B_address, E1_q_b[5]_clock_1, , , );
E1_q_b[5]_PORT_A_write_enable = VCC;
E1_q_b[5]_PORT_A_write_enable_reg = DFFE(E1_q_b[5]_PORT_A_write_enable, E1_q_b[5]_clock_0, , , E1_q_b[5]_clock_enable_0);
E1_q_b[5]_PORT_B_read_enable = VCC;
E1_q_b[5]_PORT_B_read_enable_reg = DFFE(E1_q_b[5]_PORT_B_read_enable, E1_q_b[5]_clock_1, , , );
E1_q_b[5]_clock_0 = CLOCK_50;
E1_q_b[5]_clock_1 = CLOCK_50;
E1_q_b[5]_clock_enable_0 = SW[17];
E1_q_b[5]_PORT_B_data_out = MEMORY(E1_q_b[5]_PORT_A_data_in_reg, , E1_q_b[5]_PORT_A_address_reg, E1_q_b[5]_PORT_B_address_reg, E1_q_b[5]_PORT_A_write_enable_reg, E1_q_b[5]_PORT_B_read_enable_reg, , , E1_q_b[5]_clock_0, E1_q_b[5]_clock_1, E1_q_b[5]_clock_enable_0, , , );
E1_q_b[5] = E1_q_b[5]_PORT_B_data_out[0];


--E1_q_b[6] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[6]_PORT_A_data_in = SW[6];
E1_q_b[6]_PORT_A_data_in_reg = DFFE(E1_q_b[6]_PORT_A_data_in, E1_q_b[6]_clock_0, , , E1_q_b[6]_clock_enable_0);
E1_q_b[6]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[6]_PORT_A_address_reg = DFFE(E1_q_b[6]_PORT_A_address, E1_q_b[6]_clock_0, , , E1_q_b[6]_clock_enable_0);
E1_q_b[6]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[6]_PORT_B_address_reg = DFFE(E1_q_b[6]_PORT_B_address, E1_q_b[6]_clock_1, , , );
E1_q_b[6]_PORT_A_write_enable = VCC;
E1_q_b[6]_PORT_A_write_enable_reg = DFFE(E1_q_b[6]_PORT_A_write_enable, E1_q_b[6]_clock_0, , , E1_q_b[6]_clock_enable_0);
E1_q_b[6]_PORT_B_read_enable = VCC;
E1_q_b[6]_PORT_B_read_enable_reg = DFFE(E1_q_b[6]_PORT_B_read_enable, E1_q_b[6]_clock_1, , , );
E1_q_b[6]_clock_0 = CLOCK_50;
E1_q_b[6]_clock_1 = CLOCK_50;
E1_q_b[6]_clock_enable_0 = SW[17];
E1_q_b[6]_PORT_B_data_out = MEMORY(E1_q_b[6]_PORT_A_data_in_reg, , E1_q_b[6]_PORT_A_address_reg, E1_q_b[6]_PORT_B_address_reg, E1_q_b[6]_PORT_A_write_enable_reg, E1_q_b[6]_PORT_B_read_enable_reg, , , E1_q_b[6]_clock_0, E1_q_b[6]_clock_1, E1_q_b[6]_clock_enable_0, , , );
E1_q_b[6] = E1_q_b[6]_PORT_B_data_out[0];


--E1_q_b[7] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8, Port B Logical Depth: 32, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_b[7]_PORT_A_data_in = SW[7];
E1_q_b[7]_PORT_A_data_in_reg = DFFE(E1_q_b[7]_PORT_A_data_in, E1_q_b[7]_clock_0, , , E1_q_b[7]_clock_enable_0);
E1_q_b[7]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_b[7]_PORT_A_address_reg = DFFE(E1_q_b[7]_PORT_A_address, E1_q_b[7]_clock_0, , , E1_q_b[7]_clock_enable_0);
E1_q_b[7]_PORT_B_address = BUS(read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
E1_q_b[7]_PORT_B_address_reg = DFFE(E1_q_b[7]_PORT_B_address, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_write_enable = VCC;
E1_q_b[7]_PORT_A_write_enable_reg = DFFE(E1_q_b[7]_PORT_A_write_enable, E1_q_b[7]_clock_0, , , E1_q_b[7]_clock_enable_0);
E1_q_b[7]_PORT_B_read_enable = VCC;
E1_q_b[7]_PORT_B_read_enable_reg = DFFE(E1_q_b[7]_PORT_B_read_enable, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_clock_0 = CLOCK_50;
E1_q_b[7]_clock_1 = CLOCK_50;
E1_q_b[7]_clock_enable_0 = SW[17];
E1_q_b[7]_PORT_B_data_out = MEMORY(E1_q_b[7]_PORT_A_data_in_reg, , E1_q_b[7]_PORT_A_address_reg, E1_q_b[7]_PORT_B_address_reg, E1_q_b[7]_PORT_A_write_enable_reg, E1_q_b[7]_PORT_B_read_enable_reg, , , E1_q_b[7]_clock_0, E1_q_b[7]_clock_1, E1_q_b[7]_clock_enable_0, , , );
E1_q_b[7] = E1_q_b[7]_PORT_B_data_out[0];


--C1L1 is SEG7_LUT:u1|oSEG[0]~70
C1L1 = E1_q_b[6] & !E1_q_b[5] & (E1_q_b[4] $ !E1_q_b[7]) # !E1_q_b[6] & E1_q_b[4] & (E1_q_b[5] $ !E1_q_b[7]);


--C1L2 is SEG7_LUT:u1|oSEG[1]~71
C1L2 = E1_q_b[5] & (E1_q_b[4] & (E1_q_b[7]) # !E1_q_b[4] & E1_q_b[6]) # !E1_q_b[5] & E1_q_b[6] & (E1_q_b[4] $ E1_q_b[7]);


--C1L3 is SEG7_LUT:u1|oSEG[2]~72
C1L3 = E1_q_b[6] & E1_q_b[7] & (E1_q_b[5] # !E1_q_b[4]) # !E1_q_b[6] & !E1_q_b[4] & E1_q_b[5] & !E1_q_b[7];


--C1L4 is SEG7_LUT:u1|oSEG[3]~73
C1L4 = E1_q_b[4] & (E1_q_b[5] $ !E1_q_b[6]) # !E1_q_b[4] & (E1_q_b[5] & !E1_q_b[6] & E1_q_b[7] # !E1_q_b[5] & E1_q_b[6] & !E1_q_b[7]);


--C1L5 is SEG7_LUT:u1|oSEG[4]~74
C1L5 = E1_q_b[5] & E1_q_b[4] & (!E1_q_b[7]) # !E1_q_b[5] & (E1_q_b[6] & (!E1_q_b[7]) # !E1_q_b[6] & E1_q_b[4]);


--C1L6 is SEG7_LUT:u1|oSEG[5]~75
C1L6 = E1_q_b[4] & (E1_q_b[7] $ (E1_q_b[5] # !E1_q_b[6])) # !E1_q_b[4] & E1_q_b[5] & !E1_q_b[6] & !E1_q_b[7];


--C1L7 is SEG7_LUT:u1|oSEG[6]~76
C1L7 = E1_q_b[4] & (E1_q_b[7] # E1_q_b[5] $ E1_q_b[6]) # !E1_q_b[4] & (E1_q_b[5] # E1_q_b[6] $ E1_q_b[7]);


--read_addr[0] is read_addr[0]
read_addr[0] = DFFEAS(A1L187, CLOCK_50, KEY[0],  , A1L86,  ,  ,  ,  );


--read_addr[1] is read_addr[1]
read_addr[1] = DFFEAS(A1L190, CLOCK_50, KEY[0],  , A1L86,  ,  ,  ,  );


--read_addr[2] is read_addr[2]
read_addr[2] = DFFEAS(A1L193, CLOCK_50, KEY[0],  , A1L86,  ,  ,  ,  );


--read_addr[3] is read_addr[3]
read_addr[3] = DFFEAS(A1L196, CLOCK_50, KEY[0],  , A1L86,  ,  ,  ,  );


--C4L1 is SEG7_LUT:u4|oSEG[0]~70
C4L1 = read_addr[2] & !read_addr[1] & (read_addr[0] $ !read_addr[3]) # !read_addr[2] & read_addr[0] & (read_addr[1] $ !read_addr[3]);


--C4L2 is SEG7_LUT:u4|oSEG[1]~71
C4L2 = read_addr[1] & (read_addr[0] & (read_addr[3]) # !read_addr[0] & read_addr[2]) # !read_addr[1] & read_addr[2] & (read_addr[0] $ read_addr[3]);


--C4L3 is SEG7_LUT:u4|oSEG[2]~72
C4L3 = read_addr[2] & read_addr[3] & (read_addr[1] # !read_addr[0]) # !read_addr[2] & !read_addr[0] & read_addr[1] & !read_addr[3];


--C4L4 is SEG7_LUT:u4|oSEG[3]~73
C4L4 = read_addr[0] & (read_addr[1] $ !read_addr[2]) # !read_addr[0] & (read_addr[1] & !read_addr[2] & read_addr[3] # !read_addr[1] & read_addr[2] & !read_addr[3]);


--C4L5 is SEG7_LUT:u4|oSEG[4]~74
C4L5 = read_addr[1] & read_addr[0] & (!read_addr[3]) # !read_addr[1] & (read_addr[2] & (!read_addr[3]) # !read_addr[2] & read_addr[0]);


--C4L6 is SEG7_LUT:u4|oSEG[5]~75
C4L6 = read_addr[0] & (read_addr[3] $ (read_addr[1] # !read_addr[2])) # !read_addr[0] & read_addr[1] & !read_addr[2] & !read_addr[3];


--C4L7 is SEG7_LUT:u4|oSEG[6]~76
C4L7 = read_addr[0] & (read_addr[3] # read_addr[1] $ read_addr[2]) # !read_addr[0] & (read_addr[1] # read_addr[2] $ read_addr[3]);


--read_addr[4] is read_addr[4]
read_addr[4] = DFFEAS(A1L199, CLOCK_50, KEY[0],  , A1L86,  ,  ,  ,  );


--C6L1 is SEG7_LUT:u6|oSEG[0]~70
C6L1 = SW[2] & !SW[1] & (SW[0] $ !SW[3]) # !SW[2] & SW[0] & (SW[1] $ !SW[3]);


--C6L2 is SEG7_LUT:u6|oSEG[1]~71
C6L2 = SW[1] & (SW[0] & (SW[3]) # !SW[0] & SW[2]) # !SW[1] & SW[2] & (SW[0] $ SW[3]);


--C6L3 is SEG7_LUT:u6|oSEG[2]~72
C6L3 = SW[2] & SW[3] & (SW[1] # !SW[0]) # !SW[2] & !SW[0] & SW[1] & !SW[3];


--C6L4 is SEG7_LUT:u6|oSEG[3]~73
C6L4 = SW[0] & (SW[1] $ !SW[2]) # !SW[0] & (SW[1] & !SW[2] & SW[3] # !SW[1] & SW[2] & !SW[3]);


--C6L5 is SEG7_LUT:u6|oSEG[4]~74
C6L5 = SW[1] & SW[0] & (!SW[3]) # !SW[1] & (SW[2] & (!SW[3]) # !SW[2] & SW[0]);


--C6L6 is SEG7_LUT:u6|oSEG[5]~75
C6L6 = SW[0] & (SW[3] $ (SW[1] # !SW[2])) # !SW[0] & SW[1] & !SW[2] & !SW[3];


--C6L7 is SEG7_LUT:u6|oSEG[6]~76
C6L7 = SW[0] & (SW[3] # SW[1] $ SW[2]) # !SW[0] & (SW[1] # SW[2] $ SW[3]);


--C5L1 is SEG7_LUT:u5|oSEG[0]~70
C5L1 = SW[6] & !SW[5] & (SW[4] $ !SW[7]) # !SW[6] & SW[4] & (SW[5] $ !SW[7]);


--C5L2 is SEG7_LUT:u5|oSEG[1]~71
C5L2 = SW[5] & (SW[4] & (SW[7]) # !SW[4] & SW[6]) # !SW[5] & SW[6] & (SW[4] $ SW[7]);


--C5L3 is SEG7_LUT:u5|oSEG[2]~72
C5L3 = SW[6] & SW[7] & (SW[5] # !SW[4]) # !SW[6] & !SW[4] & SW[5] & !SW[7];


--C5L4 is SEG7_LUT:u5|oSEG[3]~73
C5L4 = SW[4] & (SW[5] $ !SW[6]) # !SW[4] & (SW[5] & !SW[6] & SW[7] # !SW[5] & SW[6] & !SW[7]);


--C5L5 is SEG7_LUT:u5|oSEG[4]~74
C5L5 = SW[5] & SW[4] & (!SW[7]) # !SW[5] & (SW[6] & (!SW[7]) # !SW[6] & SW[4]);


--C5L6 is SEG7_LUT:u5|oSEG[5]~75
C5L6 = SW[4] & (SW[7] $ (SW[5] # !SW[6])) # !SW[4] & SW[5] & !SW[6] & !SW[7];


--C5L7 is SEG7_LUT:u5|oSEG[6]~76
C5L7 = SW[4] & (SW[7] # SW[5] $ SW[6]) # !SW[4] & (SW[5] # SW[6] $ SW[7]);


--C8L1 is SEG7_LUT:u8|oSEG[0]~70
C8L1 = SW[13] & !SW[12] & (SW[11] $ !SW[14]) # !SW[13] & SW[11] & (SW[12] $ !SW[14]);


--C8L2 is SEG7_LUT:u8|oSEG[1]~71
C8L2 = SW[12] & (SW[11] & (SW[14]) # !SW[11] & SW[13]) # !SW[12] & SW[13] & (SW[11] $ SW[14]);


--C8L3 is SEG7_LUT:u8|oSEG[2]~72
C8L3 = SW[13] & SW[14] & (SW[12] # !SW[11]) # !SW[13] & !SW[11] & SW[12] & !SW[14];


--C8L4 is SEG7_LUT:u8|oSEG[3]~73
C8L4 = SW[11] & (SW[12] $ !SW[13]) # !SW[11] & (SW[12] & !SW[13] & SW[14] # !SW[12] & SW[13] & !SW[14]);


--C8L5 is SEG7_LUT:u8|oSEG[4]~74
C8L5 = SW[12] & SW[11] & (!SW[14]) # !SW[12] & (SW[13] & (!SW[14]) # !SW[13] & SW[11]);


--C8L6 is SEG7_LUT:u8|oSEG[5]~75
C8L6 = SW[11] & (SW[14] $ (SW[12] # !SW[13])) # !SW[11] & SW[12] & !SW[13] & !SW[14];


--C8L7 is SEG7_LUT:u8|oSEG[6]~76
C8L7 = SW[11] & (SW[14] # SW[12] $ SW[13]) # !SW[11] & (SW[12] # SW[13] $ SW[14]);


--A1L187 is read_addr[0]~55
A1L187 = read_addr[0] $ VCC;

--A1L188 is read_addr[0]~56
A1L188 = CARRY(read_addr[0]);


--count[24] is count[24]
count[24] = DFFEAS(A1L180, CLOCK_50, KEY[0],  ,  ,  ,  , A1L86,  );


--count[18] is count[18]
count[18] = DFFEAS(A1L162, CLOCK_50, KEY[0],  ,  ,  ,  , A1L86,  );


--count[16] is count[16]
count[16] = DFFEAS(A1L156, CLOCK_50, KEY[0],  ,  ,  ,  , A1L86,  );


--A1L80 is LessThan~398
A1L80 = !count[24] & !count[18] & !count[16];


--count[12] is count[12]
count[12] = DFFEAS(A1L144, CLOCK_50, KEY[0],  ,  ,  ,  , A1L86,  );


--count[13] is count[13]
count[13] = DFFEAS(A1L147, CLOCK_50, KEY[0],  ,  ,  ,  , A1L86,  );


--count[14] is count[14]
count[14] = DFFEAS(A1L150, CLOCK_50, KEY[0],  ,  ,  ,  , A1L86,  );


--count[15] is count[15]
count[15] = DFFEAS(A1L153, CLOCK_50, KEY[0],  ,  ,  ,  , A1L86,  );